80C186EB/80C188EB Microprocessor User's Manual - CEUNES

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURESingle step priority is a special case. If an interrupt (NMI or maskable) occurs at the same instructionboundary as a single step, the interrupt vector is taken first, then is followed immediately bythe single step vector. However, the single step service routine is executed before the interruptservice routine (see Figure 2-29). If the single step service routine re-enables single step by executingthe IRET, the interrupt service routine will also be single stepped. This can severely limitthe real-time response of the CPU to an interrupt.To prevent the single-step routine from executing before a maskable interrupt, disable interruptswhile single stepping an instruction, then enable interrupts in the single step service routine. Themaskable interrupt is serviced from within the single step service routine and that interrupt serviceroutine is not single-stepped. To prevent single stepping before an NMI, the single-step serviceroutine must compare the return address on the stack to the NMI vector. If they are the same,return to the NMI service routine immediately without executing the single step service routine.NMIInstruction Trap Flag = 1Push PSW, CS, IPFetch Divide Error VectorTrap Flag = 0Push PSW, CS, IPFetch Single Step VectorExecute Single StepService RoutineIRETTrap Flag = ???A1032-0AFigure 2-29. Simultaneous NMI and Single Step InterruptsThe most complicated case is when an NMI, a maskable interrupt, a single step and another exceptionare pending on the same instruction boundary. Figure 2-30 shows how this case is prioritizedby the CPU. Note that if the single-step routine sets the Trap Flag (TF) bit before executingthe IRET instruction, the NMI routine will also be single stepped.2-48