80C186EB/80C188EB Microprocessor User's Manual - CEUNES

CLOCK GENERATION AND POWER MANAGEMENTA HOLD request from an external bus master turns on the core clock as long as HOLD is active(see Figure 5-11). The core clock restarts one CLKOUT cycle after the bus processor samplesHOLD high. The microprocessor asserts HLDA one cycle after the core clock starts. The coreclock turns off and the processor deasserts HLDA one cycle after the external bus master deassertsHOLD.1 ClockDelayCoreRestartProcessorIn HoldCore ClockShuts OffCLKOUTInternalPeripheralClockInternalCore ClockHOLDTI TI TI TI TI TI TI TI TI TI TI TIHLDAA1120-0AFigure 5-11. HOLD/HLDA During Idle ModeAs in Active mode, refresh requests will force the BIU to drop HLDA during bus hold. (For moreinformation on refresh cycles during hold, see “Refresh Operation During a Bus HOLD” on page3-41 and “Refresh Operation and Bus HOLD” on page 7-13.)5.2.1.3 Leaving Idle ModeAny unmasked interrupt or non-maskable interrupt (NMI) will return the processor to Activemode. Reset also returns the processor to Active mode, but the device loses its prior state.Any unmasked interrupt received by the core will return the processor to Active mode. Interruptrequests pass through the Interrupt Control Unit with an interrupt resolution time for mask andpriority level checking. Then, after 1½ clocks, the core clock begins toggling. It takes an additional6 CLKOUT cycles for the core to begin the interrupt vectoring sequence.5-14