80C186EB/80C188EB Microprocessor User's Manual - CEUNES

APPENDIX BINPUT SYNCHRONIZATIONMany input signals to an embedded processor are asynchronous. Asynchronous signals do not requirea specified setup or hold time to ensure the device does not incur a failure. However, asynchronoussetup and hold times are specified in the data sheet to ensure recognition. Associatedwith each of these inputs is a synchronizing circuit (see Figure B-1) that samples the asynchronoussignal and synchronizes it to the internal operating clock. The output of the synchronizingcircuit is then safely routed to the logic units.AsynchronousInput1D Q D QFirstLatch2SecondLatchSynchronizedOutputNOTES:1. First latch sample clock, can be phase 1 or phase 2 depending on pin function.2. Second latch sample clock, opposite phase of first latch sample clock(e.g., if first latch is sampled with phase 1, the second latch is sampled with phase 2).Figure B-1. Input Synchronization CircuitA1007-0AB.1 WHY SYNCHRONIZERS ARE REQUIREDEvery data latch requires a specific setup and hold time to operate properly. The duration of thesetup and hold time defines a window during which the device attempts to latch the data. If theinput makes a transition within this window, the output may not attain a stable state. The datasheet specifies a setup and hold window larger than is actually required. However, variations indevice operation (e.g., temperature, voltage) require that a larger window be specified to coverall conditions.Should the input to the data latch make a transition during the sample and hold window, the outputof the latch eventually attains a stable state. This stable state must be attained before the secondstage of synchronization requires a valid input. To synchronize an asynchronous signal, thecircuit in Figure B-1 samples the input into the first latch, allows the output to stabilize, then samplesthe stabilized value into a second latch. With the asynchronous signal resolved in this way,the input signal cannot cause an internal device failure.B-1