80C186EB/80C188EB Microprocessor User's Manual - CEUNES

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.3 INTERRUPTS AND EXCEPTION HANDLINGInterrupts and exceptions alter program execution in response to an external event or an errorcondition. An interrupt handles asynchronous external events, for example an NMI. Exceptionsresult directly from the execution of an instruction, usually an instruction fault. The user cancause a software interrupt by executing an “INTn” instruction. The CPU processes software interruptsin the same way that it handles exceptions.The 80C186 Modular Core responds to interrupts and exceptions in the same way for all deviceswithin the 80C186 Modular Core family. However, devices within the family may have differentInterrupt Control Units. The Interrupt Control Unit handles all external interrupt sources and presentsthem to the 80C186 Modular Core via one maskable interrupt request (see Figure 2-24).This discussion covers only those areas of interrupts and exceptions that are common to the80C186 Modular Core family. The Interrupt Control Unit is proliferation-dependent; see Chapter8, “Interrupt Control Unit,” for additional information.NMIMaskableInterruptRequestCPUInterruptAcknowledgeInterruptControlUnitExternalInterruptSourcesA1028-0AFigure 2-24. Interrupt Control Unit2.3.1 Interrupt/Exception ProcessingThe 80C186 Modular Core can service up to 256 different interrupts and exceptions. A 256-entryInterrupt Vector Table (Figure 2-25) contains the pointers to interrupt service routines. Each entryconsists of four bytes, which contain the Code Segment (CS) and Instruction Pointer (IP) ofthe first instruction in the interrupt service routine. Each interrupt or exception is given a typenumber, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that interrupttypes 0–31 are reserved for Intel and should not be used by an application program.2-39