80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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SERIAL COMMUNICATIONS UNITThe CPU samples BCLK on the rising edge of CLKOUT. The CLKOUT high time synchronizesthe BCLK signal. On the falling edge of CLKOUT, the synchronized BCLK signal is presentedto the baud timebase clock.CLKOUTCTS ResolvedDuring CLKOUTHigh TimeCTSTCHISTCHIHCTS(Internal)A1279-0AFigure 10-15. CTS Recognition SequenceCLKOUTBCLKTCHISTCHIH TCHISTCHIHIncrement BCNT(Internal)A1280-0AFigure 10-16. BCLK Synchronization10-19
SERIAL COMMUNICATIONS UNITBCLK is an asynchronous input. However, the pin does have setup and hold times, which guaranteerecognition at a specific CLKOUT. If the BCLK input signal has high and low times thatare both at least 1½ CLKOUT periods, than synchronization to CLKOUT is not necessary. However,when the BCLK signal has a high or a low time of less than 1½ CLKOUT periods, meetingthe setup and hold times to CLKOUT is necessary to avoid missing BCLK transitions. The maximuminput frequency to BCLK is one-half the frequency of CLKOUT (CPU operating frequency).10.3.3 Mode 0 TimingsThis section shows the timings of the TXD and RXD pins in Mode 0. In Mode 0, TXD neverfloats. When not transmitting or receiving, TXD is high. RXD floats except when transmitting acharacter.10.3.3.1 CLKOUT as Baud Timebase ClockThe behavior of the transmit/receive clock (on TXD) is governed by the value of BxCMP. Whenthe BxCMP value is greater than or equal to two. The TXD pin is low for two CLKOUT periodsand is high for (BxCMP – 1) CLKOUT periods (see Figure 10-17). BxCMP cannot be equal to aone, otherwise the serial port buffer registers (SxRBUF) will not receive the correct data.CLKOUTTXDLow For2 ClocksHigh ForN-1 ClocksRXDBIT 0BIT 1A1282-AFigure 10-17. Mode 0, BxCMP > 2For transmissions, the RXD pin changes on the next CLKOUT falling edge following a low-tohightransition on TXD. Therefore, the data on the RXD pin is guaranteed to be valid on the risingedges of TXD. Use the rising edge of TXD to latch the value on RXD. For receptions, the incomingserial data must meet the setup and hold timings with respect to the rising edge of TXD. Thesetimings can be found in the AC timings section of the data sheet.10-20
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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Page 221 and 222: INTERRUPT CONTROL UNIT3. Program th
Page 224 and 225: CHAPTER 9TIMER/COUNTER UNITThe Time
Page 226 and 227: TIMER/COUNTER UNITTimer 0 Timer 1 T
Page 228 and 229: TIMER/COUNTER UNITContinued From"A"
Page 230 and 231: TIMER/COUNTER UNITRegister Name:Reg
Page 236 and 237: TIMER/COUNTER UNITThe timer countin
Page 238 and 239: TIMER/COUNTER UNITTimer 0Serviced1I
Page 240 and 241: TIMER/COUNTER UNIT9.3.2 Synchroniza
Page 242 and 243: TIMER/COUNTER UNITlib_80186 segment
Page 244 and 245: TIMER/COUNTER UNIT$mod186nameexampl
Page 246 and 247: TIMER/COUNTER UNIT_CMPB equ word pt
Page 248: SerialCommunicationsUnit10
Page 251 and 252: SERIAL COMMUNICATIONS UNIT1 2 3 4 5
Page 253 and 254: SERIAL COMMUNICATIONS UNITThe RX ma
Page 255 and 256: SERIAL COMMUNICATIONS UNITThe Trans
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Page 265 and 266: SERIAL COMMUNICATIONS UNITThe seria
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Page 273 and 274: SERIAL COMMUNICATIONS UNITmovmovmov
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Page 277 and 278: SERIAL COMMUNICATIONS UNITMASTER186
Page 279 and 280: SERIAL COMMUNICATIONS UNIT$mod186na
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Page 283 and 284: SERIAL COMMUNICATIONS UNITcmp al, F
Page 285 and 286: SERIAL COMMUNICATIONS UNIT10-36
Page 288 and 289: CHAPTER 11INPUT/OUTPUT PORTSMany ap
Page 290 and 291: INPUT/OUTPUT PORTS11.1.2 Input Port
Page 292 and 293: INPUT/OUTPUT PORTSFrom IntegratedPe
Page 294 and 295: INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
Page 296 and 297: INPUT/OUTPUT PORTSRegister Name:Reg
Page 298 and 299: INPUT/OUTPUT PORTSRegister Name:Reg
Page 300: Math Coprocessing12
Page 303 and 304: MATH COPROCESSING12.3 THE 80C187 MA
Page 305 and 306: MATH COPROCESSINGAvailable data typ
Page 307 and 308: MATH COPROCESSING12.3.1.5 Constant
Page 309 and 310: MATH COPROCESSINGIncreasing Signifi
Page 311 and 312: MATH COPROCESSING12.4.1 Clocking th
Page 313 and 314: MATH COPROCESSINGExternalOscillator
Page 315 and 316: MATH COPROCESSING80C186Modular Core
Page 317 and 318: MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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