80C186EB/80C188EB Microprocessor User's Manual - CEUNES

CHAPTER 3BUS INTERFACE UNITThe Bus Interface Unit (BIU) generates bus cycles that prefetch instructions from memory, passdata to and from the execution unit, and pass data to and from the integrated peripheral units.The BIU drives address, data, status and control information to define a bus cycle. The start of abus cycle presents the address of a memory or I/O location and status information defining thetype of bus cycle. Read or write control signals follow the address and define the direction of dataflow. A read cycle requires data to flow from the selected memory or I/O device to the BIU. In awrite cycle, the data flows from the BIU to the selected memory or I/O device. Upon terminationof the bus cycle, the BIU latches read data or removes write data.3.1 MULTIPLEXED ADDRESS AND DATA BUSThe BIU has a combined address and data bus, commonly referred to as a time-multiplexed bus.Time multiplexing address and data information makes the most efficient use of device packagepins. A system with address latching provided within the memory and I/O devices can directlyconnect to the address/data bus (or local bus). The local bus can be demultiplexed with a singleset of address latches to provide non-multiplexed address and data information to the system.3.2 ADDRESS AND DATA BUS CONCEPTSThe programmer views the memory or I/O address space as a sequence of bytes. Memory spaceconsists of 1 Mbyte, while I/O space consists of 64 Kbytes. Any byte can contain an 8-bit dataelement, and any two consecutive bytes can contain a 16-bit data element (identified as a word).The discussions in this section apply to both memory and I/O bus cycles. For brevity, memorybus cycles are used for examples and illustration.3.2.1 16-Bit Data BusThe memory address space on a 16-bit data bus is physically implemented by dividing the addressspace into two banks of up to 512 Kbytes each (see Figure 3-1). One bank connects to the lowerhalf of the data bus and contains even-addressed bytes (A0=0). The other bank connects to theupper half of the data bus and contains odd-addressed bytes (A0=1). Address lines A19:1 selecta specific byte within each bank. A0 and Byte High Enable (BHE) determine whether one bankor both banks participate in the data transfer.3-1