80C186EB/80C188EB Microprocessor User's Manual - CEUNES

CHIP-SELECT UNITBUS READYREADY Control BitWait State Value (WS3:0)WaitStateCounterWaitStateReadyREADYA1165-0AFigure 6-7. Wait State and Ready Control FunctionsThe STOP register defines the RDY control bit to extend bus cycles beyond fifteen wait states.The RDY control bit determines whether the bus cycle should complete normally (i.e., requirebus ready) or unconditionally (i.e., ignore bus ready). Chip-selects connected to devices requiringfifteen wait states or fewer can program RDY inactive to automatically complete the bus cycle.Devices that may require more than fifteen wait states must program RDY active.A bus cycle with wait states automatically inserted cannot be shortened. A bus cycle that ignoresbus ready cannot be lengthened.6.4.6 Overlapping Chip-SelectsThe Chip-Select Unit activates all enabled chip-selects programmed to cover the same physicaladdress space. This is true if any portion of the chip-selects’ address ranges overlap (i.e., chipselects’ranges do not need to overlap completely to all go active). There are various reasons foroverlapping chip-selects. For example, a system might have a need for overlapping a portion ofread-only memory with read/write memory or copying data to two devices simultaneously.If overlapping chip-selects do not have identical wait state and bus ready programming, the Chip-Select Unit will adjust itself based on the criteria shown in Figure 6-8.6-12