80C186EB/80C188EB Microprocessor User's Manual - CEUNES

INTERRUPT CONTROL UNIT8.3.2 Interrupt Request RegisterThe Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a sourcerequests an interrupt, its Interrupt Request bit is set (without regard to whether the interrupt ismasked). The Interrupt Request bit is cleared when the interrupt is acknowledged. An externalinterrupt pin must remain asserted until its interrupt is acknowledged. Otherwise, the InterruptRequest bit will be cleared, but the interrupt will not be serviced.Register Name:Register Mnemonic:Register Function:Interrupt Request RegisterREQSTStores pending interrupt requests15 0INT3INT2INT1INT0INT4SERTMRA1206-A0BitMnemonicBit NameResetStateFunctionINT3:0, INT4SERTMRExternalInterruptsSerialChannel 0InterruptTimerInterrupt0000 0 A bit is set to indicate a pending interrupt fromthe corresponding external interrupt pin.0 This bit is set to indicate a pending interruptfrom serial channel 0 (either a receive or atransmit interrupt).0 This bit is set to indicate a pending interruptfrom one of the timers.NOTE:Reserved register bits are shown with gray shading. Reserved bits must be writtento a logic zero to ensure compatibility with future Intel products.Figure 8-7. Interrupt Request Register8-16