80C186EB/80C188EB Microprocessor User's Manual - CEUNES

PERIPHERAL CONTROL BLOCK4.3 RESERVED LOCATIONSMany locations within the Peripheral Control Block are not assigned to any peripheral. Unusedlocations are reserved. Reading from these locations yields an undefined result. If reserved registersare written (for example, during a block MOV instruction) they must be set to 0H.NOTEFailure to follow this guideline could result in incompatibilities with future80C186 Modular Core family products.4.4 ACCESSING THE PERIPHERAL CONTROL BLOCKAll communication between integrated peripherals and the Modular CPU Core occurs over a specialbus, called the F-Bus, which always carries 16-bit data. The Peripheral Control Block, likeall integrated peripherals, is always accessed 16 bits at a time.4.4.1 Bus CyclesThe processor runs an external bus cycle for any memory or I/O cycle accessing a location withinthe Peripheral Control Block. Address, data and control information is driven on the external pinsas with an ordinary bus cycle. Information returned by an external device is ignored, even if theaccess does not correspond to the location of an integrated peripheral control register. This is alsotrue for the 80C188 Modular Core family, except that word accesses made to integrated registersare performed in two bus cycles.4.4.2 READY Signals and Wait StatesThe processor generates an internal READY signal whenever an integrated peripheral is accessed.External READY is ignored. READY is also generated if an access is made to a location withinthe Peripheral Control Block that does not correspond to an integrated peripheral controlregister. For accesses to timer control and counting registers, the processor inserts one wait state.This is required to properly multiplex processor and counter element accesses to the timer controlregisters. For accesses to the remaining locations in the Peripheral Control Block, the processordoes not insert wait states.4-4