80C186EB/80C188EB Microprocessor User's Manual - CEUNES

CLOCK GENERATION AND POWER MANAGEMENTHalt CycleT4 or TI T1 TI TI TICLKOUTInternalPeripheralClockCPU Core ClockS2:0011ALEA1119-0AFigure 5-10. Entering Idle Mode5.2.1.2 Bus Operation During Idle ModeDRAM refresh requests and HOLD requests temporarily turn on the core clocks. If the processorneeds to run a refresh cycle during Idle mode, the internal core clock begins to toggle on the fallingCLKOUT edge immediately after the down-counter reaches zero. After one idle T-state, theprocessor runs the refresh cycle. As with all other bus cycles, the BIU uses the ready, wait stategeneration and chip-select circuitry as necessary for refresh cycles during Idle mode. There is oneidle T-state after T4 before the internal core clock shuts off again.5-13