80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-4. Mnemonic Encoding Matrix (Right Half)x8 x9 xA xB xC xD xE xFORb,f,r/mSBBb,f,r/mSUBb,f,r/mCMPb,f,r/mDECAXPOPAXPUSHORw,f,r/mSBBw,f,r/mSUBw,f,r/mCMPw,f,r/mDECCXPOPCXIMULORb,t,r/mSBBb,t,r/mSUBb,t,r/mCMPb,t,r/mDECDXPOPDXPUSHw,iw,ib,iJS JNS JP/JPEORw,t,r/mSBBw,t,r/mSUBw,t,r/mCMPw,t,r/mDECBXPOPBXIMULw,iJNP/JPOORb,iSBBb,iSUBb,iCMPb,iDECSPPOPSPINSbJL/JNGEORw,iSBBw,iSUBw,iCMPw,iDECBPPOPBPINSwJNL/JGEPUSHCSPUSHDSSEG=CSSEG=DSDECSIPOPSIOUTSbJLE/JNGPOPDSDASAASDECDIPOPDIOUTSwJNLE/JG0x1x2x3x4x5x6x7xMOVb,f,r/mMOVw,f,r/mMOVb,t,r/mMOVw,t,r/mMOVsr,f,r/mLEA MOVsr,t,r/mPOPr/mCBW CWD CALL WAIT PUSHF POPF SAHF LAHFL,DTEST TEST STOS STOS LODS LODS SCAS SCASb,ia w,iaMOV MOV MOV MOV MOV MOV MOV MOVi→AX i→CX i→DX i→BX i→SP i→BP i→SI i→DIENTER LEAVE RET RET INT INT INTO IRETl(i+SP) l type 3 (any)ESC ESC ESC ESC ESC ESC ESC ESC01234567CALL JMP JMP JMP IN IN OUT OUT8x9xAxBxCxDxExCLC STC CLI STI CLS STD Grp2b,r/mGrp2w,r/mFxNOTE: Table D-5 defines abbreviations used in this matrix. Shading indicates reserved opcodes.D-21
INSTRUCTION SET OPCODES AND CLOCK CYCLESTable D-5. Abbreviations for Mnemonic Encoding MatrixAbbr Definition Abbr Definition Abbr Definition Abbr Definitionb byte operation ia immediate to accumulator m memory t to CPU registerd direct id indirect r/m EA is second byte v variablef from CPU register is immediate byte, sign extended si short intrasegment w word operationi immediate l long (intersegment) sr segment register z zeroByte 2 Immed Shift Grp1 Grp2mod 000 r/m ADD ROL TEST INCmod 001 r/m OR ROR — DECmod 010 r/m ADC RCL NOT CALL idmod 011 r/m SBB RCR NEG CALL l, idmod 100 r/m AND SHL/SAL MUL JMP idmod 101 r/m SUB SHR IMUL JMP i, idmod 110 r/m XOR — DIV PUSHmod 111 r/m CMP SAR IDIV —mod and r/m determine the Effective Address (EA) calculation. See Table D-1 for definitions.D-22
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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Page 390 and 391: APPENDIX DINSTRUCTION SET OPCODESAN
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Page 412: Index
Page 415 and 416: INDEXand T-states, 3-9data phase, 3
Page 417 and 418: INDEXarithmetic instructions, 2-19-
Page 419 and 420: INDEXblock diagram, 3-15implementat
Page 421: INDEXWWait statesand bus cycles, 3-
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