80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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CHIP-SELECT UNITAddress1ReadyFlashDataUCS1MB1023KUCSCEProcessorActive ForTop 1 KByteMemoryMap0NOTE:1. 15 Wait states automatically inserted. Bus READY must be provided.A1162-0AFigure 6-4. UCS Reset Configuration6.4 PROGRAMMINGTwo registers, START and STOP, determine the operating characteristics of each chip-select.The Peripheral Control Block defines the location of the Chip-Select Unit registers. Table 6-1lists the registers and their associated programming names.Table 6-1. Chip-Select Unit RegistersSTART RegisterMnemonicSTOP RegisterMnemonicChip-Select AffectedGCS0ST GCS0SP GCS0GCS1ST GCS1SP GCS1GCS2ST GCS2SP GCS2GCS3ST GCS3SP GCS3GCS4ST GCS4SP GCS4GCS5ST GCS5SP GCS5GCS6ST GCS6SP GCS6GCS7ST GCS7SP GCS7UCSST UCSSP UCSLCSST LCSSP LCS6-5
CHIP-SELECT UNITThe START register (Figure 6-5) defines the starting address and the wait state requirements. TheSTOP register (Figure 6-6) defines the ending address and the bus ready, bus cycle and enablerequirements.6.4.1 Initialization SequenceChip-selects do not have to be initialized in any specific order. However, the following guidelineshelp prevent a system failure.1. Initialize local memory chip-selects2. Initialize local peripheral chip-selects3. Perform local diagnostics4. Initialize off-board memory and peripheral chip-selects5. Complete system diagnosticsAn unmasked interrupt or NMI must not occur until the interrupt vector addresses have been writtento memory. Failure to prevent an interrupt from occurring during initialization will cause asystem failure. Use external logic to generate the chip-select if interrupts cannot be masked priorto initialization.6-6
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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Page 117 and 118: BUS INTERFACE UNITThe WAIT instruct
Page 119 and 120: BUS INTERFACE UNITCLKOUTHOLD124HLDA
Page 121 and 122: BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
Page 123 and 124: BUS INTERFACE UNITCLKOUTHOLD12345HL
Page 126: Peripheral ControlBlock4
Page 129 and 130: PERIPHERAL CONTROL BLOCKRegister Na
Page 131 and 132: PERIPHERAL CONTROL BLOCK4.3 RESERVE
Page 133 and 134: PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
Page 135 and 136: PERIPHERAL CONTROL BLOCK4-8
Page 138 and 139: CHAPTER 5CLOCK GENERATION AND POWER
Page 140 and 141: CLOCK GENERATION AND POWER MANAGEME
Page 158: Chip-Select Unit6
Page 161 and 162: CHIP-SELECT UNIT27C25674AC138A1:13A
Page 163: CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
Page 167 and 168: CHIP-SELECT UNITRegister Name:Regis
Page 169 and 170: CHIP-SELECT UNIT6.4.2 Start Address
Page 171 and 172: CHIP-SELECT UNITBUS READYREADY Cont
Page 173 and 174: CHIP-SELECT UNITTable 6-3 lists exa
Page 175 and 176: CHIP-SELECT UNITREADYALEA19:16AD15:
Page 177 and 178: CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
Page 179 and 180: CHIP-SELECT UNIT; DATA SEGMENTDATAS
Page 182 and 183: CHAPTER 7REFRESH CONTROL UNITThe Re
Page 184 and 185: REFRESH CONTROL UNITRefresh Control
Page 186 and 187: REFRESH CONTROL UNIT7.5 REFRESH BUS
Page 188 and 189: REFRESH CONTROL UNIT7.7 PROGRAMMING
Page 190 and 191: REFRESH CONTROL UNITRegister Name:R
Page 192 and 193: REFRESH CONTROL UNITRegister Name:R
Page 194 and 195: REFRESH CONTROL UNITmov dx, RFBASEm
Page 196: Interrupt ControlUnit8
Page 199 and 200: INTERRUPT CONTROL UNITTimer 0 Timer
Page 201 and 202: INTERRUPT CONTROL UNITInterrupt sou
Page 203 and 204: INTERRUPT CONTROL UNIT8.2.2.1 Prior
Page 205 and 206: INTERRUPT CONTROL UNITINTINT08259Ao
Page 207 and 208: INTERRUPT CONTROL UNIT8.2.6 Edge an
Page 209 and 210: INTERRUPT CONTROL UNITTable 8-3. In
Page 211 and 212: INTERRUPT CONTROL UNIT.Register Nam
Page 213 and 214: INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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