80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNITPhysical Implementationof the Address Space for8-Bit Systems1 MByteFFFFFFFFFEPhysical Implementationof the Address Space for16-Bit Systems512 KBytes 512 KBytesFFFFFFFFFEFFFFDFFFFC210531420A19:0 D7:0 A19:1 D15:8 BHED7:0A0A1100-0AFigure 3-1. Physical Data Bus ModelsByte transfers to even addresses transfer information over the lower half of the data bus (see Figure3-2). A0 low enables the lower bank, while BHE high disables the upper bank. The data valuefrom the upper bank is ignored during a bus read cycle. BHE high prevents a write operation fromdestroying data in the upper bank.Byte transfers to odd addresses transfer information over the upper half of the data bus (see Figure3-2). BHE low enables the upper bank, while A0 high disables the lower bank. The data valuefrom the lower bank is ignored during a bus read cycle. A0 high prevents a write operation fromdestroying data in the lower bank.To access even-addressed 16-bit words (two consecutive bytes with the least-significant byte atan even address), information is transferred over both halves of the data bus (see Figure 3-3).A19:1 select the appropriate byte within each bank. A0 and BHE drive low to enable both bankssimultaneously.Odd-addressed word accesses require the BIU to split the transfer into two byte operations (seeFigure 3-4). The first operation transfers data over the upper half of the bus, while the second operationtransfers data over the lower half of the bus. The BIU automatically executes the two-bytesequence whenever an odd-addressed word access is performed.3-2