80C186EB/80C188EB Microprocessor User's Manual - CEUNES

CLOCK GENERATION AND POWER MANAGEMENTAfter execution of the IRET (interrupt return) instruction in the interrupt service routine, theCS:IP will point to the instruction following the HALT. Interrupt execution does not modify thePower Control Register. Unless the programmer intentionally reprograms the register after exitingIdle mode, the processor will re-enter Idle mode at the next HLT instruction.Like an unmasked interrupt, an NMI will return the core to Active mode from Idle mode. It takestwo CLKOUT cycles to restart the core clock after an NMI occurs. The NMI signal does not needthe mask and priority checks that a maskable interrupt does. This results in a considerable differencein clock restart time between an NMI and an unmasked interrupt. The core begins the interruptresponse six cycles after the core clock restarts when it fetches the NMI vector from location00008H. NMI does not clear the IDLE bit in the Power Control Register.Resetting the microprocessor will return the device to Active mode. Unlike interrupts, a resetclears the Power Control Register. Execution begins as it would following a warm reset (see “Resetand Clock Synchronization” on page 5-6).5.2.1.4 Example Idle Mode Initialization CodeExample 5-1 illustrates programming the Power Control Register and entering Idle mode uponHLT. The interrupts from the serial port and timers are not masked. Assume that the serial portconnects to a keyboard controller. At every keystroke, the keyboard sends a data byte, and theprocessor wakes up to service the interrupt. After acting on the keystroke, the core will go backinto Idle mode. The example excludes the actual keystroke processing.5-15