80C186EB/80C188EB Microprocessor User's Manual - CEUNES

INTERRUPT CONTROL UNITInterrupt sources can be masked on the basis of their priority. The Priority Mask register masksall interrupts with priorities lower than its programmed value. After reset, the Priority Mask registercontains priority seven, which effectively enables all interrupts. The programmer can thenprogram the register with any valid priority level.8.1.1.3 Interrupt NestingWhen entering an interrupt handler, the CPU pushes the Processor Status Word onto the stackand clears the Interrupt Enable bit. The processor enters all interrupt handlers with maskable interruptsdisabled. Maskable interrupts remain disabled until either the IRET instruction restoresthe Interrupt Enable bit or the programmer explicitly enables interrupts. Enabling maskable interruptswithin an interrupt handler allows interrupts to be nested. Otherwise, interrupts are processedsequentially; one interrupt handler must finish before another executes.The simplest way to use the Interrupt Control Unit is without nesting. The operation and servicingof all sources of maskable interrupts is straightforward. However, the application tradeoff is thatan interrupt handler will finish executing even if a higher priority interrupt occurs. This can addconsiderable latency to the higher priority interrupt.In the simplest terms, the Interrupt Control Unit asserts the maskable interrupt request to the CPU,waits for the interrupt acknowledge, then presents the interrupt type of the highest priority unmaskedinterrupt to the CPU. The CPU then executes the interrupt handler for that interrupt. Becausethe interrupt handler never sets the Interrupt Enable bit, it can never be interrupted.The function of the Interrupt Control Unit is more complicated with interrupt nesting. In this case,an interrupt can occur during execution of an interrupt handler. That is, one interrupt can preemptanother. Two rules apply for interrupt nesting:• An interrupt source cannot preempt interrupts of higher priority.• An interrupt source cannot preempt itself. The interrupt handler must finish executingbefore the interrupt is serviced again. (Special Fully Nested Mode is an exception. See“Special Fully Nested Mode” on page 8-8.)8.2 FUNCTIONAL OPERATIONThis section covers the process in which the Interrupt Control Unit receives interrupts and assertsthe maskable interrupt request to the CPU.8-4