80C186EB/80C188EB Microprocessor User's Manual - CEUNES

INPUT/OUTPUT PORTSRegister Name:Register Mnemonic:Register Function:Port Pin State RegisterPxPIN (P1PIN, P2PIN)Reads the logic state at a port pin.15 0PP7PP6PP5PP4PP3PP2PP1PP0A1315-0ABitMnemonicBit NameResetStateFunctionPP7:0Port PinState 7:0XXXXHReading the Port Pin State register returns thelogic state present on the associated pin.NOTE:Reserved register bits are shown with gray shading. Reserved bits must be writtento a logic zero to ensure compatibility with future Intel products.Figure 11-8. Port Pin State Register (PxPIN)11.2.5 Initializing the I/O PortsThe state of the I/O ports following a reset is as follows:• Port 1 is configured for peripheral function (general-purpose chip-selects, GCS7:0).• Port 2 is configured for peripheral function. The direction of each pin is the default directionfor the peripheral function (e.g., P2.1/TXD1 is an output, P2.5/BCLK0 is an input). SeeTable 11-2 on page 11-7 for details.There are no set rules for initializing the I/O ports. The Port Data Latch should be programmedbefore selecting a pin as an output port (to prevent unknown Port Data Latch values from reachingthe pins).11-11