80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNIT3.5.4 HALT Bus CycleSuspending the CPU reduces device power consumption and potentially reduces interrupt latencytime. The HLT instruction initiates two events:1. Suspends the Execution Unit.2. Instructs the BIU to execute a HALT bus cycle.The Idle or Powerdown power management mode (or the absence of both of them, known as ActiveMode) affects the operation of the bus HALT cycle. The effects relating to BIU operationand the HALT bus cycle are described in this chapter. Chapter 4, “Clock Generation and PowerManagement,” discusses the concepts of Active, Idle and Powerdown power management modes.After executing a HALT bus cycle, the BIU suspends operation until one of the following eventsoccurs:• An interrupt is generated.• A bus HOLD is generated (except when Powerdown mode is enabled).• A refresh request is generated (except when Powerdown mode is enabled).Figure 3-25 shows the operation of a HALT bus cycle. The address/data bus either floats or drivesduring T1, depending on the next bus cycle to be executed by the BIU. Under most instructionsequences, the BIU floats the address/data bus because the next operation would most likely bean instruction prefetch. However, if the HALT occurs just after a bus write operation, the address/databus drives either data or address information during T1. A19:16 continue to drive theprevious bus cycle information under most instruction sequences (otherwise, they drive the nextprefetch address). The BIU always operates in the same way for any given instruction sequence.The Chip-Select Unit prevents a programmed chip-select from going active during a HALT buscycle. However, chip-selects generated by external decoder circuits must be disabled for HALTbus cycles.3-28