80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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MATH COPROCESSINGExternalOscillatorLatchA15:0AD15:0ALECLKOUT80C186ModularCoreENA1 A2CMD0CMD1CKMCLK80C18712BufferT OED15:8RESOUTWRRESETNPWRBufferD7:0RDNPRDBUSYBUSYOETERRORERRORPEREQPEREQNCSNPS1CSDENNPS2DT/RD15:0A1255-01Figure 12-2. 80C186 Modular Core Family/80C187 System Configuration12-9
MATH COPROCESSING12.4.1 Clocking the 80C187The microprocessor and math coprocessor operate asynchronously, and their clock rates may differ.The 80C187 has a CKM pin that determines whether it uses the input clock directly or dividedby two. Direct clocking works up to 12.5 MHz, which makes it convenient to feed the clock inputfrom the microprocessor’s CLKOUT pin. Beyond 12.5 MHz, the 80C187 must use a multiplyby-twoclock input up to a maximum of 32 MHz. The microprocessor and the math coprocessorhave correct timing relationships, even with operation at different frequencies.12.4.2 Processor Bus Cycles Accessing the 80C187Data transfers between the microprocessor and the 80C187 occur through the dedicated, 16-bitI/O ports shown in Table 12-7. When the processor encounters a numerics opcode, it first writesthe opcode to the 80C187. The 80C187 decodes the instruction and passes elementary instructioninformation (Opcode Status Word) back to the processor. Since the 80C187 is a slave processor,the Modular Core processor performs all loads and stores to memory. Including the overhead inthe microprocessor’s microcode, each data transfer between memory and the 80C187 (via the microprocessor)takes at least 17 processor clocks.Table 12-7. 80C187 I/O Port AssignmentsI/O Address Read Definition Write Definition00F8H Status/Control Opcode00FAH Data Data00FCH Reserved CS:IP, DS:EA00FEH Opcode Status ReservedThe microprocessor cannot process any numerics (ESC) opcodes alone. If the CPU encounters anumerics opcode when the Escape Trap (ET) bit in the Relocation Register is a zero and the80C187 is not present, its operation is indeterminate. Even the FINIT/FNINIT initialization instruction(used in the past to test the presence of a coprocessor) fails without the 80C187. If anapplication offers the 80C187 as an option, problems can be prevented in one of three ways:• Remove all numerics (ESC) instructions, including code that checks for the presence of the80C187.• Use a jumper or switch setting to indicate the presence of the 80C187. The program caninterrogate the jumper or switch setting and branch away from numerics instructions whenthe 80C187 socket is empty.• Trick the microprocessor into predictable operation when the 80C187 socket is empty. Thefix is placing pull-up or pull-down resistors on certain data and handshaking lines so theCPU reads a recognizable Opcode Status Word. This solution requires a detailed knowledgeof the interface.12-10
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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Page 288 and 289: CHAPTER 11INPUT/OUTPUT PORTSMany ap
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Page 296 and 297: INPUT/OUTPUT PORTSRegister Name:Reg
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Page 300: Math Coprocessing12
Page 303 and 304: MATH COPROCESSING12.3 THE 80C187 MA
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Page 307 and 308: MATH COPROCESSING12.3.1.5 Constant
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Page 315 and 316: MATH COPROCESSING80C186Modular Core
Page 317 and 318: MATH COPROCESSING$mod186$modc187nam
Page 320 and 321: CHAPTER 13ONCE MODEONCE (pronounced
Page 322: 80C186 InstructionSet Additions and
Page 325 and 326: 80C186 INSTRUCTION SET ADDITIONS AN
Page 336 and 337: APPENDIX BINPUT SYNCHRONIZATIONMany
Page 338: Instruction SetDescriptionsC
Page 341 and 342: INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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