80C186EB/80C188EB Microprocessor User's Manual - CEUNES

OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREString instructions automatically update the SI register, the DI register, or both, before processingthe next string element. The Direction Flag (DF) determines whether the index registers are autoincremented(DF = 0) or auto-decremented (DF = 1). The processor adjusts the DI, SI, or bothregisters by one for byte strings or by two for word strings.If a repeat prefix is used, the count register (CX) is decremented by one after each repetition ofthe string instruction. The CX register must be initialized to the number of repetitions before thestring instruction is executed. If the CX register is 0, the string instruction is not executed andcontrol goes to the following instruction.Table 2-8. String Instruction Register and Flag UseSIDICXAL/AXDFZFIndex (offset) for source stringIndex (offset) for destination stringRepetition counterScan valueDestination for LODSSource for STOSDirection Flag0 = auto-increment SI, DI1 = auto-decrement SI, DIScan/compare terminator2.2.1.5 Program Transfer InstructionsThe contents of the Code Segment (CS) and Instruction Pointer (IP) registers determine the instructionexecution sequence in the 80C186 Modular Core family. The CS register contains thebase address of the current code segment. The Instruction Pointer register points to the memorylocation of the next instruction to be fetched. In most operating conditions, the next instructionwill already have been fetched and will be waiting in the CPU instruction queue. Program transferinstructions operate on the IP and CS registers. Changing the contents of these registers causesnormal sequential operation to be altered. When a program transfer occurs, the queue no longercontains the correct instruction. The Bus Interface Unit obtains the next instruction from memoryusing the new IP and CS values. It then passes the instruction directly to the Execution Unit andbegins refilling the queue from the new location.The 80C186 Modular Core family offers four groups of program transfer instructions (see Table2-9). These are unconditional transfers, conditional transfers, iteration control instructions and interrupt-relatedinstructions.2-23