80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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CLOCK GENERATION AND POWER MANAGEMENTCLKINCLKOUTUCS, LCSGCS7:0T0OUTT1OUTTXD1:0,NPSHLDA, ALESINT1A19:16AD15:0S2:0, RDWR, DENDT / RLOCKRESINRESOUTMinimum RESINlow time 4 CLKOUTperiods.RESINhigh tofirst busactivity 7CLKOUTperiods.A1133-0AFigure 5-7. Warm Reset WaveformAt the second falling CLKOUT edge after the internal clocks resynchronize, the processor deassertsRESOUT. Bus activity starts seven CLKOUT periods after recognition of RESIN in the logichigh state. If an alternate bus master asserts HOLD during reset, the processor immediatelyasserts HLDA and will not prefetch instructions.5-9
CLOCK GENERATION AND POWER MANAGEMENTCLKINRESINRESYNC(Internal)1354CLKOUTRESOUT26NOTES:1. Setup of RESIN to falling CLKIN.2. RESOUT goes active.3. RESIN allowed to go inactive after minimum 4 CLKOUT cycles.4. RESYNC pulse generated.5. RESYNC pulse drives CLKOUT low, resynchronizing the clock generator.6. RESOUT goes inactive on the second falling CLKOUT edge following CLKOUT resynchronization.Figure 5-8. Clock Synchronization at ResetA1117-0A5.2 POWER MANAGEMENTMany VLSI devices available today use dynamic circuitry. A dynamic circuit uses a capacitor(usually parasitic gate or diffusion capacitance) to store information. The stored charge decaysover time due to leakage currents in the silicon. If the device does not use the stored informationbefore it decays, the state of the entire device may be lost. Circuits must periodically refresh dynamicRAMs, for example, to ensure data retention. Any microprocessor that has a minimumclock frequency has dynamic logic. On a dynamic microprocessor, if you stop or slow the clock,the dynamic nodes within it begin discharging. With a long enough delay, the processor is likelyto lose its present state, needing a reset to resume normal operation.An 80C186 Modular Core microprocessor is fully static. The CPU stores its current state inflip-flops, not capacitive nodes. The clock signal to both the CPU core and the peripherals canstop without losing any internal information, provided the design maintains power. When theclock restarts, the device will execute from its previous state. When the processor is inactive forsignificant periods, special power management hardware takes advantage of static operation toachieve major power savings.5-10
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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Page 99 and 100: BUS INTERFACE UNITAn idle bus state
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Page 105 and 106: BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
Page 107 and 108: BUS INTERFACE UNIT3.5.4 HALT Bus Cy
Page 109 and 110: BUS INTERFACE UNITCLKOUTT1 TI TIALE
Page 111 and 112: BUS INTERFACE UNITCLKOUTALES2:0AD15
Page 113 and 114: BUS INTERFACE UNITCLKOUTNMI/INTxNot
Page 115 and 116: BUS INTERFACE UNITALEProcessorA19:1
Page 117 and 118: BUS INTERFACE UNITThe WAIT instruct
Page 119 and 120: BUS INTERFACE UNITCLKOUTHOLD124HLDA
Page 121 and 122: BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
Page 123 and 124: BUS INTERFACE UNITCLKOUTHOLD12345HL
Page 126: Peripheral ControlBlock4
Page 129 and 130: PERIPHERAL CONTROL BLOCKRegister Na
Page 131 and 132: PERIPHERAL CONTROL BLOCK4.3 RESERVE
Page 133 and 134: PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
Page 135 and 136: PERIPHERAL CONTROL BLOCK4-8
Page 138 and 139: CHAPTER 5CLOCK GENERATION AND POWER
Page 140 and 141: CLOCK GENERATION AND POWER MANAGEME
Page 158: Chip-Select Unit6
Page 161 and 162: CHIP-SELECT UNIT27C25674AC138A1:13A
Page 163 and 164: CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
Page 165 and 166: CHIP-SELECT UNITThe START register
Page 167 and 168: CHIP-SELECT UNITRegister Name:Regis
Page 169 and 170: CHIP-SELECT UNIT6.4.2 Start Address
Page 171 and 172: CHIP-SELECT UNITBUS READYREADY Cont
Page 173 and 174: CHIP-SELECT UNITTable 6-3 lists exa
Page 175 and 176: CHIP-SELECT UNITREADYALEA19:16AD15:
Page 177 and 178: CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
Page 179 and 180: CHIP-SELECT UNIT; DATA SEGMENTDATAS
Page 182 and 183: CHAPTER 7REFRESH CONTROL UNITThe Re
Page 184 and 185: REFRESH CONTROL UNITRefresh Control
Page 186 and 187: REFRESH CONTROL UNIT7.5 REFRESH BUS
Page 188 and 189: REFRESH CONTROL UNIT7.7 PROGRAMMING
Page 190 and 191: REFRESH CONTROL UNITRegister Name:R
Page 192 and 193: REFRESH CONTROL UNITRegister Name:R
Page 194 and 195: REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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