80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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Introduction1
Page 1 and 2: 80C186EB/80C188EBMicroprocessorUser
Page 3 and 4: Information in this document is pro
Page 5 and 6: CONTENTS2.3.2 Software Interrupts .
Page 7 and 8: CONTENTS6.4.4 Enabling and Disablin
Page 9 and 10: CONTENTS10.2.2 Asynchronous Mode Pr
Page 11 and 12: CONTENTSFIGURESFigurePage2-1 Simpli
Page 13 and 14: CONTENTSFIGURESFigurePage6-9 Using
Page 15 and 16: CONTENTSTableTABLESPage1-1 Comparis
Page 17: CONTENTSEXAMPLESExamplePage5-1 Init
Page 21 and 22: INTRODUCTIONThe 80C186 Modular Core
Page 23 and 24: INTRODUCTIONTable 1-2. Related Docu
Page 25 and 26: INTRODUCTIONIf you encounter any di
Page 28 and 29: CHAPTER 2OVERVIEW OF THE 80C186 FAM
Page 30 and 31: OVERVIEW OF THE 80C186 FAMILY ARCHI
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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CHAPTER 3BUS INTERFACE UNITThe Bus
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BUS INTERFACE UNITY + 1X + 1Even By
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BUS INTERFACE UNIT(X + 1)First Bus
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BUS INTERFACE UNIT3.3.1 16-Bit Bus
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BUS INTERFACE UNITThe address/statu
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BUS INTERFACE UNITT4or TI T1 T2CLKO
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BUS INTERFACE UNIT3.4.2 Data PhaseF
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BUS INTERFACE UNITT1 T2 T3 TW TW T4
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BUS INTERFACE UNITWait State Module
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BUS INTERFACE UNITT2 T3 TWT4CLKOUT1
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BUS INTERFACE UNITT OE , T ACC and
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BUS INTERFACE UNITT1 T2 T3 T4CLKOUT
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BUS INTERFACE UNITThe minimum devic
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BUS INTERFACE UNITFigure 3-24 shows
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BUS INTERFACE UNITAfter several TI
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BUS INTERFACE UNITCLKOUTHOLDHLDAAD1
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BUS INTERFACE UNITCLKOUTALE8 1/2 cl
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BUS INTERFACE UNIT3.6.1 Buffering t
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BUS INTERFACE UNITAD15:88ADENGCS0OE
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BUS INTERFACE UNITIn general, prefi
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BUS INTERFACE UNITThe major factors
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BUS INTERFACE UNIT+5+5PRED Q Latche
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BUS INTERFACE UNIT6. Internal error
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CHAPTER 4PERIPHERAL CONTROL BLOCKAl
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PERIPHERAL CONTROL BLOCKTable 4-1.
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PERIPHERAL CONTROL BLOCK4.4.3 F-Bus
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PERIPHERAL CONTROL BLOCKAs an examp
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Clock Generation andPower Managemen
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6CHIP-SELECT UNITEvery syst
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CHIP-SELECT UNITStopValueIgnore Sto
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CHIP-SELECT UNITAddress1ReadyFlashD
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNITIn the previous equ
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CHIP-SELECT UNITNoAnyREADY = 1WaitM
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CHIP-SELECT UNITThe GCS chip-select
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CHIP-SELECT UNIT$ TITLE (Chip-Selec
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CHIP-SELECT UNIT;SET UP CHIP SELECT
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Refresh Control Unit7
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REFRESH CONTROL UNIT7.1 THE ROLE OF
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REFRESH CONTROL UNITThe BIU does no
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REFRESH CONTROL UNITCLKOUTT4 T1 T2
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNIT$mod186nameexam
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REFRESH CONTROL UNITT1 T1 T1 T1 T1
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CHAPTER 8INTERRUPT CONTROL UNITThe
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INTERRUPT CONTROL UNITThe Interrupt
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INTERRUPT CONTROL UNIT8.2.1 Typical
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INTERRUPT CONTROL UNIT8.2.2.2 Inter
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INTERRUPT CONTROL UNIT8.2.4 Interru
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INTERRUPT CONTROL UNITInterrupt pre
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT8.3.3 Interru
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Timer/Counter Unit9
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TIMER/COUNTER UNITT0 InT1 InTransit
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TIMER/COUNTER UNITStartTimerEnabled
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TIMER/COUNTER UNITWhen configured f
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNIT9.2.2 Clock Sourc
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TIMER/COUNTER UNITTable 9-2. Timer
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TIMER/COUNTER UNITThe input pins fo
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TIMER/COUNTER UNIT$mod186name examp
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TIMER/COUNTER UNITsti;enable interr
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TIMER/COUNTER UNITpop dx ;restore s
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TIMER/COUNTER UNIT9-24
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CHAPTER 10SERIAL COMMUNICATIONS UNI
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SERIAL COMMUNICATIONS UNITReception
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SERIAL COMMUNICATIONS UNITSxTBUFFro
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SERIAL COMMUNICATIONS UNITTXD/RXD1
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SERIAL COMMUNICATIONS UNIT10.2 PROG
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITDue to in
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SERIAL COMMUNICATIONS UNITThe CPU s
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SERIAL COMMUNICATIONS UNIT10.3.3.2
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SERIAL COMMUNICATIONS UNIT10.5 SERI
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SERIAL COMMUNICATIONS UNITmov dx, S
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SERIAL COMMUNICATIONS UNITmov dx, P
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITmov dx, S
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SERIAL COMMUNICATIONS UNITDisconnec
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SERIAL COMMUNICATIONS UNIT$mod186na
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Input/Output Ports11
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTSFrom PortDirectio
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INPUT/OUTPUT PORTS11.2.1 Port Contr
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTS11.3 PROGRAMMING
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CHAPTER 12MATH COPROCESSINGThe 80C1
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MATH COPROCESSING12.3.1.1 Data Tran
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MATH COPROCESSING12.3.1.3 Compariso
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MATH COPROCESSING12.3.2 80C187 Data
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSINGBus cycles involvi
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MATH COPROCESSING12.4.4 Exception T
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MATH COPROCESSING$mod186name exampl
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ONCE Mode13
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ONCE MODE13-2
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APPENDIX A80C186 INSTRUCTION SETADD
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80C186 INSTRUCTION SET ADDITIONS AN
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InputSynchronizationB
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INPUT SYNCHRONIZATIONA synchronizat
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APPENDIX CINSTRUCTION SET DESCRIPTI
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSNEGNOPN
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INSTRUCTION SET DESCRIPTIONSSHRSTCS
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Instruction SetOpcodes and ClockCyc
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INSTRUCTION SET OPCODES AND CLOCK C
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INDEX80C187 Math Coprocessor, 12-2-
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INDEXData transfers, 3-1-3-6instruc
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INDEXlogical, 2-10, 2-12offset valu
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INDEXSHR instruction, A-9SI registe
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80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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