80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNITWait State ModuleCS1CS2EnableOutREADYALECLKOUTLoadClockA1081-0AFigure 3-16. Generating a Normally Ready Bus SignalThe READY input has two major timing concerns that can affect whether a normally ready ornormally not-ready signal may be required. Two latches capture the state of the READY input(see Figure 3-14 on page 3-15). The first latch captures READY on the phase 2 clock edge. Thesecond latch captures READY and the result of first latch on the phase 1 clock edge. The followingitems define the requirements of the READY input to meet ready or not-ready bus conditions.• The bus is ready if both of these two conditions are true:— READY is active prior to the phase 2 clock edge, and— READY remains active after the phase 1 clock edge.• The bus is not-ready if either of these two conditions is true:— READY is inactive prior to the phase 2 clock edge, or— READY is inactive prior to the phase 1 clock edge.A normally not-ready system must generate a valid READY input at phase 2 of T2 to preventwait states. If it cannot, then running without wait states requires a normally ready system. Figure3-17 illustrates the timing necessary to prevent wait states in a normally not-ready system. Figure3-17 also shows how to terminate a bus cycle with wait states in a normally not-ready system.3-17