80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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INTERRUPT CONTROL UNITRegister Name:Register Mnemonic:Interrupt Control Register (cascadable pins)I0CON, I1CONRegister Function: Control register for the cascadable externalinterrupt pins15 0SFNMCASLVLMSKPM2PM1PM0A1215-A0BitMnemonicBit NameResetStateFunctionSFNMCASSpecialFullyNestedModeCascadeMode0 Set to enable special fully nested mode.0 Set to enable cascade mode.LVL Level-trigger 0 Selects the interrupt triggering mode:0 = edge triggering1 = level triggering.The LVL bit must be set when external 8259Asare cascaded into the Interrupt Control Unit.MSKPM2:0InterruptMaskPriorityLevel1 Clear to enable interrupts from this source.111 Defines the priority level for this source.NOTE:Reserved register bits are shown with gray shading. Reserved bits must be writtento a logic zero to ensure compatibility with future Intel products.Figure 8-6. Interrupt Control Register for Cascadable Interrupt Pins8-15
INTERRUPT CONTROL UNIT8.3.2 Interrupt Request RegisterThe Interrupt Request register (Figure 8-7) has one bit for each interrupt source. When a sourcerequests an interrupt, its Interrupt Request bit is set (without regard to whether the interrupt ismasked). The Interrupt Request bit is cleared when the interrupt is acknowledged. An externalinterrupt pin must remain asserted until its interrupt is acknowledged. Otherwise, the InterruptRequest bit will be cleared, but the interrupt will not be serviced.Register Name:Register Mnemonic:Register Function:Interrupt Request RegisterREQSTStores pending interrupt requests15 0INT3INT2INT1INT0INT4SERTMRA1206-A0BitMnemonicBit NameResetStateFunctionINT3:0, INT4SERTMRExternalInterruptsSerialChannel 0InterruptTimerInterrupt0000 0 A bit is set to indicate a pending interrupt fromthe corresponding external interrupt pin.0 This bit is set to indicate a pending interruptfrom serial channel 0 (either a receive or atransmit interrupt).0 This bit is set to indicate a pending interruptfrom one of the timers.NOTE:Reserved register bits are shown with gray shading. Reserved bits must be writtento a logic zero to ensure compatibility with future Intel products.Figure 8-7. Interrupt Request Register8-16
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
Page 161 and 162: CHIP-SELECT UNIT27C25674AC138A1:13A
Page 163 and 164: CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
Page 165 and 166: CHIP-SELECT UNITThe START register
Page 167 and 168: CHIP-SELECT UNITRegister Name:Regis
Page 169 and 170: CHIP-SELECT UNIT6.4.2 Start Address
Page 171 and 172: CHIP-SELECT UNITBUS READYREADY Cont
Page 173 and 174: CHIP-SELECT UNITTable 6-3 lists exa
Page 175 and 176: CHIP-SELECT UNITREADYALEA19:16AD15:
Page 177 and 178: CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
Page 179 and 180: CHIP-SELECT UNIT; DATA SEGMENTDATAS
Page 182 and 183: CHAPTER 7REFRESH CONTROL UNITThe Re
Page 184 and 185: REFRESH CONTROL UNITRefresh Control
Page 186 and 187: REFRESH CONTROL UNIT7.5 REFRESH BUS
Page 188 and 189: REFRESH CONTROL UNIT7.7 PROGRAMMING
Page 190 and 191: REFRESH CONTROL UNITRegister Name:R
Page 192 and 193: REFRESH CONTROL UNITRegister Name:R
Page 194 and 195: REFRESH CONTROL UNITmov dx, RFBASEm
Page 196: Interrupt ControlUnit8
Page 199 and 200: INTERRUPT CONTROL UNITTimer 0 Timer
Page 201 and 202: INTERRUPT CONTROL UNITInterrupt sou
Page 203 and 204: INTERRUPT CONTROL UNIT8.2.2.1 Prior
Page 205 and 206: INTERRUPT CONTROL UNITINTINT08259Ao
Page 207 and 208: INTERRUPT CONTROL UNIT8.2.6 Edge an
Page 209 and 210: INTERRUPT CONTROL UNITTable 8-3. In
Page 211: INTERRUPT CONTROL UNIT.Register Nam
Page 215 and 216: INTERRUPT CONTROL UNIT8.3.4 Priorit
Page 217 and 218: INTERRUPT CONTROL UNITReading the P
Page 219 and 220: INTERRUPT CONTROL UNITRegister Name
Page 221 and 222: INTERRUPT CONTROL UNIT3. Program th
Page 224 and 225: CHAPTER 9TIMER/COUNTER UNITThe Time
Page 226 and 227: TIMER/COUNTER UNITTimer 0 Timer 1 T
Page 228 and 229: TIMER/COUNTER UNITContinued From"A"
Page 230 and 231: TIMER/COUNTER UNITRegister Name:Reg
Page 236 and 237: TIMER/COUNTER UNITThe timer countin
Page 238 and 239: TIMER/COUNTER UNITTimer 0Serviced1I
Page 240 and 241: TIMER/COUNTER UNIT9.3.2 Synchroniza
Page 242 and 243: TIMER/COUNTER UNITlib_80186 segment
Page 244 and 245: TIMER/COUNTER UNIT$mod186nameexampl
Page 246 and 247: TIMER/COUNTER UNIT_CMPB equ word pt
Page 248: SerialCommunicationsUnit10
Page 251 and 252: SERIAL COMMUNICATIONS UNIT1 2 3 4 5
Page 253 and 254: SERIAL COMMUNICATIONS UNITThe RX ma
Page 255 and 256: SERIAL COMMUNICATIONS UNITThe Trans
Page 257 and 258: SERIAL COMMUNICATIONS UNIT5. At the
Page 259 and 260: SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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