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not a physical interface. Rather, an electrical IC-level interface is part of the Gigabit
controller card. The reason for the GMII is the need for a wider data path between
the RSand the Gigabit physical coding sublayer (PCS). The GMII uses two 8-wire
data paths (one TX (transmit) and one RX (receive) 8-wire path) for data
transmission. On the TX side, MAC data is transmitted in octets (8-bit groups) from
the RS to the PCS. Over the 8-wire GMII TX path, at a rate of 1 octet/cycle with a
clock rate of 125MHz, providing a total data transmission rate of 1,000Mbps. After
the octet reaches the PCS end of the GMII path, the octet is encoded into a 8B/10B
symbol. On the RX side, PCS decodes the octet and transmits it to the RS sublayer
at the equivalent TX transmission rate. The GMII can also operate at 2.5 and 25MHz
to be backward compatible with 10Mbps and 100Mbps operation. The GMII is also
responsible for relaying control information (such as collision detection) to the MAC.
Figure 4.18 illustrates the Gigabit Ethernet MAC and PHY interfaces.
Figure 4.18. 1,000Mbps Ethernet, data link (MAC),
NOTE
and physical layer (PHY) interfaces.
Where Gigabit Ethernet differs from its predecessors is its preference for full-duplex
operation, and its operational orientation (in terms of operational media
preference—that is, fiber optic cable) toward network backbone and high-speed
server applications.