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DTE status indica<strong>to</strong>rs. Most integrated DSU/CSU provide a serial configuration and<br />

testing interface and support SNMP management.<br />

High-Speed Digital Transport: T-Carrier (DS-3/DS-4)<br />

and SONET/SDH (OC1/OC3)<br />

To meet <strong>the</strong> growing demand for voice and data communications services,<br />

telephone carriers require interoffice trunk lines that can provide transport rates<br />

and DS0 destinations beyond that of <strong>the</strong> primary rate (DS1) trunk carrier circuit. To<br />

provide <strong>the</strong>se transport services, one of two digital transport solutions is employed:<br />

T-carrier or SONET.<br />

DS3 Service over T3<br />

To provide DS3 service over T-carrier, an asynchronous T3 transport circuit is used.<br />

It is asynchronous transport because timing is derived from <strong>the</strong> two output circuits<br />

independently from one ano<strong>the</strong>r. T3 transmission circuits operate over microwave<br />

radio, multimode fiber, satellite, and coaxial cable (for short distances only). The<br />

formation of a T3 utilizes 28 T1 circuits, multiplexed <strong>to</strong>ge<strong>the</strong>r using a two-step<br />

multiplexing process called M13 multiplexing.<br />

The first step multiplexes <strong>the</strong> 28 T1s in<strong>to</strong> seven T2 circuits. Each T2 channel is<br />

constructed out of four T1s and consists of <strong>the</strong> 6.176Mbps from <strong>the</strong> four T1s, plus<br />

136KBs of framing and stuff bits <strong>to</strong> accommodate <strong>the</strong> timing differences between<br />

<strong>the</strong> four T1s. This is called plesiochronous multiplexing, where two or more<br />

bitstreams operating at <strong>the</strong> same bit rate are controlled by different timing sources.<br />

The actual T2 frame is formed by interleaving <strong>the</strong> T1 bits <strong>to</strong>ge<strong>the</strong>r. It consists of four<br />

subframes, each consisting of six blocks of 49 bits each. Figure 5.5 illustrates this<br />

process.<br />

Figure 5.5. T1-<strong>to</strong>-T2 multiplexing.<br />

The second step takes <strong>the</strong> seven T2 circuits and multiplexes <strong>the</strong>m <strong>to</strong>ge<strong>the</strong>r <strong>to</strong> form<br />

<strong>the</strong> T3 circuit. The combination of <strong>the</strong> seven T2 circuits is also a plesiochronous

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