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• Switch backplane—Also referred <strong>to</strong> as a switch matrix. This is<br />

<strong>the</strong> interconnect used by <strong>the</strong> switch ports <strong>to</strong> establish<br />

connection paths and exchange packets.<br />

• Switching logic—Contains four elements:<br />

o A CPU manages <strong>the</strong> operation of <strong>the</strong> switch and packet<br />

forwarding.<br />

o The switch logic module is generally an<br />

Application-Specific Integrated Circuit (ASIC) that<br />

performs Layer 2 address lookups, SAT table creation,<br />

and sets up and tears down port connections across <strong>the</strong><br />

backplane as needed for packet forwarding. ASIC-based<br />

switches are <strong>the</strong> predominant type of switch on <strong>the</strong><br />

market, mainly because <strong>the</strong>y are less expensive and<br />

perform better than using RISC or CISC processors and<br />

software. Because <strong>the</strong> use of ASIC technology enables <strong>the</strong><br />

switch, you can perform all <strong>the</strong> switch operations in<br />

hardware. The downside is that <strong>the</strong> switch vendor needs<br />

<strong>to</strong> update or re-spin <strong>the</strong> ASIC every time a new<br />

technology arrives that cannot be handled with software.<br />

This can become an annoyance because often you need <strong>to</strong><br />

buy a new switch for any significant technology or feature<br />

change.<br />

o DRAM is used for packet buffer and SAT s<strong>to</strong>rage. Two<br />

different approaches are used <strong>to</strong> implement port<br />

buffering: dedicated and shared. With dedicated buffering,<br />

each port has its own dedicated DRAM buffer. With shared<br />

buffering, all <strong>the</strong> ports use a common memory pool.<br />

Dedicated buffering is faster, but is prone <strong>to</strong> overflows<br />

(which essentially halts packet processing) because <strong>the</strong><br />

buffers are often not very large (32KB is <strong>the</strong> average size).<br />

The shared approach is slower but more efficient because<br />

<strong>the</strong> pool is shared <strong>to</strong> allow <strong>the</strong> ports that need <strong>the</strong> buffer<br />

<strong>to</strong> get it. With <strong>the</strong> dedicated model, <strong>the</strong> buffer goes<br />

unused. Packet buffer size is very important <strong>to</strong> <strong>the</strong><br />

efficient operation of <strong>the</strong> switch <strong>the</strong> more <strong>the</strong> better.<br />

Inadequate port buffering results in packet loss,<br />

excessive collisions, and overall poor switch performance.<br />

o Flash memory is used <strong>to</strong> hold <strong>the</strong> switch's operating<br />

system and switch configuration information. Older<br />

switches can use EPROMs <strong>to</strong> hold <strong>the</strong> switch's OS and<br />

NVRAM <strong>to</strong> hold configuration information. This, however,<br />

is quite a drag when <strong>the</strong> time comes for an OS upgrade<br />

because <strong>the</strong> PROM usually needs <strong>to</strong> be replaced.

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