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His<strong>to</strong>rically, due <strong>to</strong> ATM's faster operating rates, ATM switch<br />

backplanes had significantly higher bandwidth ratings than traditional<br />

LAN switches. This is really not <strong>the</strong> case <strong>to</strong>day. Like a LAN switch, <strong>the</strong><br />

ATM switch backplane needs <strong>to</strong> have enough bandwidth <strong>to</strong> support<br />

<strong>the</strong> simultaneous operation of its ports at <strong>the</strong> highest operating rate.<br />

ATM interfaces do not support full-duplex operation, so <strong>the</strong> required<br />

switch backplane can be calculated quite easily by adding <strong>the</strong> number<br />

of ports, multiplying <strong>the</strong> result by <strong>the</strong>ir highest operating rate, and<br />

<strong>the</strong>n dividing <strong>the</strong> sum by two. If <strong>the</strong> result is less than <strong>the</strong> switch's<br />

rated backplane, blocking will result when all <strong>the</strong> switch ports are<br />

active.<br />

An ATM switch logic controller consists of <strong>the</strong> same basic elements<br />

found in a LAN switch logic controller: a CPU, a switch logic module,<br />

DRAM, and Flash. Due <strong>to</strong> ATM's fast operating rate and guaranteed<br />

QoS demands, cellprocessing is ideally performed in hardware.<br />

Therefore, <strong>the</strong> use of ASIC-based switch logic modules is quite<br />

common. However, where most ATM switches tend <strong>to</strong> fall short is in<br />

<strong>the</strong> area of buffer space. ATM switches commonly use a shared DRAM<br />

buffer <strong>to</strong> s<strong>to</strong>re cells <strong>the</strong>y cannot process. If <strong>the</strong> switch comes under<br />

heavy load and <strong>the</strong> buffers overflow, <strong>the</strong> switch will drop cells. This, in<br />

turn, forces <strong>the</strong> transmitting applications <strong>to</strong> retransmit <strong>the</strong> lost<br />

packets, which contributes even fur<strong>the</strong>r <strong>to</strong> <strong>the</strong> switch's overloaded<br />

condition. With ATM switches, buffer sizes often dictate how well <strong>the</strong><br />

switch will perform. The general rule is "bigger is better." In <strong>the</strong> end,<br />

<strong>the</strong> speed of <strong>the</strong> ASIC and <strong>the</strong> backplane are irrelevant if <strong>the</strong> switch<br />

cannot actually process <strong>the</strong> cells.<br />

ATM Cell Forwarding<br />

ATM cells are forwarded using a technique derived from X.25 and<br />

Frame Relay known as label swapping. With label swapping, each cell<br />

has a logical connection identifier (LCID). In ATM's case, <strong>the</strong> Virtual<br />

Path Identifier (VPI) and <strong>the</strong> Virtual Channel Identifier (VCI) fields in<br />

<strong>the</strong> cell header are <strong>the</strong> cell's LCID. The VPI/VCI are used individually<br />

or collectively <strong>to</strong> determine which port <strong>the</strong> cell exits from. Each ATM<br />

switch in <strong>the</strong> connection path has its own mapping table that contains<br />

<strong>the</strong> local VPI/VCI mappings for each port and <strong>the</strong>ir relations <strong>to</strong> PVC<br />

and SVC connections handled by <strong>the</strong> switch. Cells are <strong>the</strong>n forwarded<br />

between ATM switch ports based on <strong>the</strong>ir VPI/VCI. Once <strong>the</strong> cell<br />

reaches <strong>the</strong> ATM switch output port, a new VIP/VCI is inserted in<strong>to</strong> <strong>the</strong><br />

cell header and <strong>the</strong> cell is forwarded on <strong>to</strong> <strong>the</strong> next switch. This<br />

process is repeated until <strong>the</strong> cell reaches its final destination.

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