i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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NP-Voltage controlled with Schmitt Trigger The signal integrity of a NP-voltage controlled delay element can be improved by using a Schmitt trigger in series which converts the slow edges to fast edges [15]. However, as in many other delay elements, the slow edges due to the NP voltage controlled delay element will cause short circuit power dissipation at the input stage of the Schmitt trigger. N-Voltage Controlled Figure 6-5: NP-Voltage Controlled delay element with Schmitt Trigger For an N-Voltage controlled delay element, varying the control voltage Vn changes the delay by changing the discharging current. When there is a rise transition at the input, the first inverter discharges through the control transistor path while the second inverter charges the 84
output normally. The signal integrity is similar to a cascaded inverter case. The power consumption will be similar to the cascaded inverter case, except for the additional control voltage transistors, which contribute additional power due to the additional diffusion capacitance [15]. Figure 6-6 below shows the N-voltage controlled delay element. P-Voltage Controlled Figure 6-6: N-Voltage Controlled delay element Another variant of the NP-voltage controlled delay element is the P-voltage controlled delay element. The control voltage Vp changes the delay by changing the charging current. The analysis of the P-voltage controlled delay element is similar to the N-voltage and NP-voltage controlled delay elements. Figure 6-7 below shows the P-voltage controlled delay element. 85
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A PHYSICAL IMPLEMENTATION WITH CUST
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A PHYSICAL IMPLEMENTATION WITH CUST
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4.0 ASIC DESIGN FLOW ..............
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6.5.5 Characterization Results for
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LIST OF TABLES Table 5-1: ALU Modul
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LIST OF FIGURES Figure 1-1: SuperCI
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Figure 5-20: BIGFABRIC Logical Diag
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Figure 7-4: EEPROM Erase Physical O
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ACKNOWLEDGEMENTS “Many, O Jehovah
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1.0 INTRODUCTION Technological adva
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Property) block. The physical desig
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the thesis proposes a power gated m
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2.0 SUPERCISC RECONFIGURABLE HARDWA
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The specifications of the hardware
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INP2 selects from ALU1, ALU2, ALU3
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3.0 POWER ESTIMATION The need for e
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3.1.1 Static Power Consumption Stat
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Internal Power Internal Power is th
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Switching activity Generation Switc
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Figure 3-4: Leakage Power definitio
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The entire array contains informati
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3.3.2 Calculation of Fall Power Fig
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Figure 3-10: Off-state leakage Powe
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Figure 4-1 : Typical ASIC Design Fl
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Figure 4-2: ASIC Physical Design Fl
Page 51 and 52: 4.1.2 Powerplanning Power planning
Page 53 and 54: created in the design. Routing feed
Page 55 and 56: 4.1.7 Routing Once the standard cel
Page 57 and 58: Table 5-1: ALU Module Specification
Page 59 and 60: Table 5-2 shows the important speci
Page 61 and 62: the basic parameters are specified,
Page 63 and 64: direction have to be aligned on the
Page 65 and 66: ALU Stripe Pin Assignment The “ib
Page 67 and 68: 5.2.1 MUX Module Specifications As
Page 69 and 70: Figure 5-12: MUX Stripe Logical Dia
Page 71 and 72: MUX initialization routine The MUX
Page 73 and 74: Table 5-10: MUX Stripe Pin Placemen
Page 75 and 76: Figure 5-15: FINALMUX Module Logica
Page 77 and 78: Table 5-12: Final MUX Stripe Specif
Page 79 and 80: pins in the FINALMUX stripe is plac
Page 81 and 82: larger system. Figure 5-22 shows th
Page 83 and 84: Figure 5-20: BIGFABRIC Logical Diag
Page 85 and 86: Figure 5-22: Place and Routed BIGFA
Page 87 and 88: BIGFABRIC Stripe Pin Assignment As
Page 89 and 90: The SPEF file can be generated usin
Page 91 and 92: 5.5.1 Power Results for ADPCM Encod
Page 93 and 94: 5.5.3 Power Results for IDCT Row Be
Page 95 and 96: 5.5.5 Power Results for Sobel Bench
Page 97 and 98: 6.0 DELAY ELEMENTS FOR LOW POWER FA
Page 99 and 100: Transmission gate with Schmitt Trig
Page 101: PMOS transistors have their gate in
Page 105 and 106: m-Transistor Cascaded Inverter This
Page 107 and 108: 6.2 LOW POWER FABRIC USING DELAY EL
Page 109 and 110: The use of delay elements in the ha
Page 111 and 112: 6.3.2 Dynamic Triggering Scheme A d
Page 113 and 114: Figure 6-16 shows the shunt current
Page 115 and 116: td1 is the delay in discharging nod
Page 117 and 118: δt is the regeneration time of the
Page 119 and 120: transistors, they are active low si
Page 121 and 122: delay elements are enabled on a log
Page 123 and 124: charge sharing happens between the
Page 125 and 126: Figure 6-23: AND gate to generate D
Page 127 and 128: uffer with a drive capacity of 640f
Page 129 and 130: Cell Rise Delay The Cell Rise Delay
Page 131 and 132: Fall Transition Time The time taken
Page 133 and 134: 6.5.6 Characterization Results for
Page 135 and 136: 7.0 EEPROM CIRCUIT DESIGN EEPROM (E
Page 137 and 138: 7.1.1 Erase Operation Figure 7-3: I
Page 139 and 140: 7.1.2 Write Operation Figure 7-6: I
Page 141 and 142: Figure 7-9: IV Characteristics of a
Page 143 and 144: The current source IFN, resistor RT
Page 145 and 146: Figure 7-11: HSPICE Description of
Page 147 and 148: 7.2.1 Ramp Generator The ramp gener
Page 149 and 150: 7.2.4 Column Latch for Bitlines inp
Page 151 and 152: 7.2.5 Power Multiplexer Figure 7-16
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The inverter pair connected to the
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7.2.7 Memory Bank Architecture Figu
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7.2.8 Memory Bank Simulation Figure
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(Vpp) and a normal voltage (Vdd), t
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8.1.2 Dynamic Decoder The address d
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8.3 POWER-ON RESET One problem with
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Figure 8-6 shows the modified charg
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To study the impact of the power co
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9.0 CONCLUSION For this thesis, I h
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definitions, metal layer resistance
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APPENDIX B element standard cell ch
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$k=-1; $j=-1; $i=-1; foreach $ load
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$FALL_START_8 = $OFFSET8 + $ONTIME;
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if ($#rise_power_6 == -1) { # $modi
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$modified_spice_array[$i] = $temp2;
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@fall_power_9 = grep(/fall_power9/,
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print MEASHANDLE $_; print ENERGYHA
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} print MEASHANDLE " "; print ENERG
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set VAL [expr "$NUMBER_OF_MODULES_P
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set DIE_WIDTH_STRIPE [expr {($MODUL
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#*************************PLACING i
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preassignPin stripe $PIN_NAME -loc
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set X_LOC [expr {($X _LOC -( 31*$OU
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#Module related details set NUMBER_
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set X_LOC 0 set Y_LOC 41.2 for {set
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Table D 1 (Continued) 506.232fF 0.0
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121.344fF 0.076ns 0.4634 0.2277 570
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Table D 5 (Continued) 9.48 0. 516 0
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Table D 7: Characterization data fo
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Transi tion Table D 9: Characteriza
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[13] M.F. Aburdene, J. Zheng, and R
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i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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