i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

Switching activity Generation
Switching activity generation is an important step in event based power estimation.
Switching activity of the circuit is estimated by running a Modelsim simulation of the design
using predetermined input vectors. The toggling of nets in the design is captured by the VCD
(Value Change Dump) file. While generating the VCD file, the delays after place and route of
the design can be annotated using the SDF (Standard Delay Format) file. The SDF file contains
the delays of all the cells and interconnects in the design. The SDF file can be generated by the
place and route tool like SoC Encounter using the command ‘delayCal’.
Although, the back-annotation of the SDF file is optional, back-annotation gives an
accurate estimate of the delays in the design and is therefore highly recommended. Before the
design has been placed and routed, an approximate estimate of the delay can be obtained by
using the synthesized netlist along with wire load models. The use of SDF file is much better
than using wire load models as the SDF file contains the actual calculated delays from the place
and route information [38].
Power Profile Generation
The power profile can be generated by running a prime power script on the design which
uses the VCD file. Using the VCD file which contains the information on all toggling nets in the
design, dynamic energy consumed in every transition is computed. The static power consumed
by every cell in the design is given by the standard cell library description provided by the
technology vendor. The total power consumed by the design is the sum of the dynamic and static
power consumed. The parasitic information extracted from the place and route tool can be
annotated using the SPEF (Standard Parasitic Extraction Format) file generated by the tool.
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