i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
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4.1.3 Partitioning a design<br />
Partitioning the design is the process of breaking the top level design into modules which can be<br />
placed and routed independently. Modules specified as partitions are designs which can be<br />
worked upon independently. The place and routed partitions can be finally integrated into the top<br />
level design to make the complete chip. Modules that are not specified as partitions are<br />
automatically a part of the top level design and get placed and routed at the place and route phase<br />
of the top level design.<br />
4.1.4 Routing Feedthrough<br />
After the design has been partitioned, the entire metal stack along with the transistor area is<br />
reserved for the partition for its placement and routing. The top level design by default does not<br />
have any metal area reserved for routing nets that cross the partitions. This leads to routing<br />
congestions in a chip which has multiple partitions and the top level design has nets that run<br />
across partitions.<br />
Figure 4-6 shows nets from partition-A getting connected to partition-C. If an inter-<br />
partition space is available as shown in Figure 4-6 the tool might route the nets around partition-<br />
B. However, if there are too many nets that need to be routed, the inter-partition space might get<br />
congested and may result in DRC violations. To avoid such disastrous situations, it is necessary<br />
to have specific areas in the metal layers reserved for top level routing. Such reserved metal<br />
areas are called routing feedthroughs. Figure 4-7 shows routing when routing feedthroughs are<br />
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