i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

6.2 LOW POWER FABRIC USING DELAY ELEMENTS
Delay elements can be used in the SuperCISC Reconfigurable Hardware Fabric to save a
significant amount of glitching power. As the entire hardware fabric uses a combinational flow,
timing differences between two paths can cause glitches at the output of the combinational block.
These glitches contribute significant amount of power in the operation of the device. Delay
elements are used to enable the latches at the data inputs to the functional unit. The latches are
enabled at time t0 which is the maximum of the all the data path delays to the functional unit.
Thus freezing of the gate inputs until all data inputs become available minimizes the glitch
power. Thus delay elements can be used to minimize the power.
For an example consider the combinational circuit shown in Figure 6-11 . The adders
have a propagation delay of 1.2ns, multipliers have a delay of 4ns and subtractors have a delay of
1.25ns. The critical path on the left side of the final multiplier M1 is 5.25ns and on the right side
is 4ns. The final multiplier switches continuously during the entire duration of 9.25ns,which is
the sum of the maximum critical path delay of the operands (5.25ns) and the propagation delay
of the multiplier M1(4ns) itself.
Figure 6-12 shows the latches (L) that are introduced at the inputs to the operands of the
multiplier M1. The latches L are enabled by a 5ns delay element. As the inputs to the multiplier
M1 are enabled only after 5ns, M1 switches for 0.25ns due to the left input operand and for 4ns
due to its own propagation delay. Thus the total switching time is only 4.25ns. As shown, the
delay element has reduced the switching time from 9.25ns to 4.25ns, hence reducing the
glitching power consumption of the system.
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