i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

Figure 6-16 shows the shunt current condition when the D transitions from a logic low to
a logic high state. When D transitions from a logic low to a logic high, the left thyristor turns on
while the right thyristor turns off. These simultaneous actions cause a shunt current path from
Vdd to ground. This shunt current can be avoided by turning off the right thyristor once node Q~
reaches Vdd. The Penable signal is delayed version of signal Q~ which can be used to turn of the
right thyristor and turn on the left thyristor for the next cycle. Figure 6-17 shows the shunt
current condition when D transitions from a logic high to a logic low state. The Nenable signal is
a delayed version of signal Q which can be used to turn off the left thyristor and turn on the right
thyristor. The Nenable prevents the shunt current during a transition from a high state to a low
state on the D input.
Figure 6-16: CMOS Thyristor Shunt current when D transitions to a high
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