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4.0 ASIC DESIGN FLOW
A standard ASIC design flow starts right from system specification definition. Once the
specifications of the system are clear, specifications are partitioned into logical modules. The
logical modules are then implemented using a hardware description language such as VHDL or
Verilog. The design is then tested for functional correctness using functional simulations. Once
the modules are implemented, the design is synthesized to obtain the gate level netlist [8]. The
design flow from specification definition to synthesis is typically called the front end design of
the ASIC.
Once the design has been synthesized, the next step in the design process is the physical
design including the placement and routing of the design to obtain the GDS file which contains
the polygon information of the layout. The GDS file is handed over to the foundary for the chip
to be fabricated. Once the chip has been manufactured, it is typically packaged. The packaged
chip is tested for its datasheet specifications before being shipped to the customer. The part of
the design flow from the synthesized netlist to the GDS file is called the backend design of an
ASIC. The test process once the chip is packaged is typically called the post-silicon validation
process. Figure 4-1 below shows the typical ASIC design flow right from input specifications all
the way to GDSII generation [8].
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