i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

BIGFABRIC Stripe Pin Assignment
As the “big_fabric” is the top level chip which gets integrated into a system, it is
necessary that the RHF interface is easier. To make it easier the input and output pins are made
accessible from the top of the chip. The placement of the FINALMUX stripe is near the top of
the chip, making the output pins easier to access. The “ibm_pinassign_chip_alu_ctrl.tcl” is used
to assign the ALU related control pins to the top level chip. The
“ibm_pinassign_chip_alu_data.tcl” is used to assign ALU related data pins which act as inputs to
the SuperCISC reconfigurable hardware fabric. The “ibm_pinassign_chip_mux_ctrl.tcl” is used
to assign MUX related control pins to the fabric. The “ibm_pinassign_chip_finalmux_ctrl.tcl” is
used to assign FINALMUX related control pins. The “ibm_pinassign_chip_finalmux_data.tcl” is
used to assign the output related pins of the FINALMUX stripe which are actually the outputs of
the hardware fabric.
5.5 POWER ANALYSIS OF THE CHIP
Power Analysis was completed using Synopsys Prime Power to estimate the power consumed by
the chip after placement and routing. As described in section 4, post place and route information
was captured using the SDF (Standard Delay Format) and the SPEF (Standard Parasitic
Extraction Format) files. The SDF captures the delay incurred due to interconnects in the design.
The SPEF captures the parasitic capacitance and resistance of the nets.
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