i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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TABLE OF CONTENTS ACKNOWLEDGEMENTS ..................................................................................................... xvii 1.0 INTRODUCTION ........................................................................................................ 1 1.1 STATEMENT OF THE PROBLEM ................................................................. 6 2.0 SUPERCISC RECONFIGURABLE HARDWARE FABRIC ................................ 7 2.1 ARCHITECTURE OF THE SUPERCISC RHF .............................................. 8 2.2 ARITHMETIC AND LOGIC UNIT (ALU) ...................................................... 9 2.3 INTERCONNECT MULTIPLEXER STRUCTURE (MUX) ....................... 10 2.4 FINAL MULTIPLEXER STRUCTURE (FINALMUX) ............................... 11 3.0 POWER ESTIMATION ............................................................................................ 13 3.1 POWER DISSIPATION TERMINOLOGIES ............................................... 13 3.1.1 Static Power Consumption ........................................................................... 15 3.1.2 Dynamic Power Consumption ...................................................................... 16 3.2 PRIMEPOWER POWER ESTIMATION FLOW ......................................... 17 3.2.1 Prime Power’s Event Based Power Estimation Flow ................................. 18 3.2.2 Calculation of Static Power Dissipated using Prime Power ...................... 20 3.2.3 Calculation of Dynamic Power Dissipated using Prime Power ................. 21 3.3 POWER ESTIMATION USING HSPICE ...................................................... 23 3.3.1 Calculation of Rise Power ............................................................................. 24 3.3.2 Calculation of Fall Power.............................................................................. 25 3.3.3 Calculation of On-State Leakage ................................................................. 26 3.3.4 Calculation of Off-State Leakage ................................................................. 26 iv
4.0 ASIC DESIGN FLOW ............................................................................................... 28 4.1 PHYSICAL DESIGN FLOW ........................................................................... 30 4.1.1 Floorplanning ................................................................................................. 30 4.1.2 Powerplanning ............................................................................................... 33 4.1.3 Partitioning a design ...................................................................................... 34 4.1.4 Routing Feedthrough .................................................................................... 34 4.1.5 Pin Assignment .............................................................................................. 36 4.1.6 Placement ....................................................................................................... 36 4.1.7 Routing ........................................................................................................... 37 5.0 PHYSICAL IMPLEMENTATION OF THE SUPERCISC RHF ......................... 38 5.1 DESIGN OF THE ALU STRIPE ..................................................................... 38 5.1.1 ALU Module Specifications .......................................................................... 38 5.1.2 ALU Stripe Specifications ............................................................................. 40 5.1.3 ALU Stripe Automation Scripts ................................................................... 42 5.2 DESIGN OF THE MULTIPLEXER STRIPE ................................................ 48 5.2.1 MUX Module Specifications ......................................................................... 49 5.2.2 MUX Stripe Specifications ............................................................................ 50 5.2.3 MUX Stripe Automation Scripts .................................................................. 52 5.3 DESIGN OF THE FINALMUX STRIPE ........................................................ 56 5.3.1 FINALMUX Module Specifications............................................................. 56 5.3.2 FINALMUX Stripe Specifications ............................................................... 58 5.3.3 FINALMUX Stripe Automation Scripts ..................................................... 59 5.4 DESIGN OF THE BIGFABRIC ...................................................................... 61 v
Page 1 and 2: A PHYSICAL IMPLEMENTATION WITH CUST
Page 3: A PHYSICAL IMPLEMENTATION WITH CUST
Page 7 and 8: 6.5.5 Characterization Results for
Page 9 and 10: LIST OF TABLES Table 5-1: ALU Modul
Page 11 and 12: LIST OF FIGURES Figure 1-1: SuperCI
Page 13 and 14: Figure 5-20: BIGFABRIC Logical Diag
Page 15 and 16: Figure 7-4: EEPROM Erase Physical O
Page 17 and 18: ACKNOWLEDGEMENTS “Many, O Jehovah
Page 19 and 20: 1.0 INTRODUCTION Technological adva
Page 21 and 22: Property) block. The physical desig
Page 23 and 24: the thesis proposes a power gated m
Page 25 and 26: 2.0 SUPERCISC RECONFIGURABLE HARDWA
Page 27 and 28: The specifications of the hardware
Page 29 and 30: INP2 selects from ALU1, ALU2, ALU3
Page 31 and 32: 3.0 POWER ESTIMATION The need for e
Page 33 and 34: 3.1.1 Static Power Consumption Stat
Page 35 and 36: Internal Power Internal Power is th
Page 37 and 38: Switching activity Generation Switc
Page 39 and 40: Figure 3-4: Leakage Power definitio
Page 41 and 42: The entire array contains informati
Page 43 and 44: 3.3.2 Calculation of Fall Power Fig
Page 45 and 46: Figure 3-10: Off-state leakage Powe
Page 47 and 48: Figure 4-1 : Typical ASIC Design Fl
Page 49 and 50: Figure 4-2: ASIC Physical Design Fl
Page 51 and 52: 4.1.2 Powerplanning Power planning
Page 53 and 54: created in the design. Routing feed
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4.1.7 Routing Once the standard cel
Page 57 and 58:
Table 5-1: ALU Module Specification
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Table 5-2 shows the important speci
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the basic parameters are specified,
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direction have to be aligned on the
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ALU Stripe Pin Assignment The “ib
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5.2.1 MUX Module Specifications As
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Figure 5-12: MUX Stripe Logical Dia
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MUX initialization routine The MUX
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Table 5-10: MUX Stripe Pin Placemen
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Figure 5-15: FINALMUX Module Logica
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Table 5-12: Final MUX Stripe Specif
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pins in the FINALMUX stripe is plac
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larger system. Figure 5-22 shows th
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Figure 5-20: BIGFABRIC Logical Diag
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Figure 5-22: Place and Routed BIGFA
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BIGFABRIC Stripe Pin Assignment As
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The SPEF file can be generated usin
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5.5.1 Power Results for ADPCM Encod
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5.5.3 Power Results for IDCT Row Be
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5.5.5 Power Results for Sobel Bench
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6.0 DELAY ELEMENTS FOR LOW POWER FA
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Transmission gate with Schmitt Trig
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PMOS transistors have their gate in
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output normally. The signal integri
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m-Transistor Cascaded Inverter This
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6.2 LOW POWER FABRIC USING DELAY EL
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The use of delay elements in the ha
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6.3.2 Dynamic Triggering Scheme A d
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Figure 6-16 shows the shunt current
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td1 is the delay in discharging nod
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δt is the regeneration time of the
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transistors, they are active low si
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delay elements are enabled on a log
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charge sharing happens between the
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Figure 6-23: AND gate to generate D
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uffer with a drive capacity of 640f
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Cell Rise Delay The Cell Rise Delay
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Fall Transition Time The time taken
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6.5.6 Characterization Results for
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7.0 EEPROM CIRCUIT DESIGN EEPROM (E
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7.1.1 Erase Operation Figure 7-3: I
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7.1.2 Write Operation Figure 7-6: I
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Figure 7-9: IV Characteristics of a
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The current source IFN, resistor RT
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Figure 7-11: HSPICE Description of
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7.2.1 Ramp Generator The ramp gener
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7.2.4 Column Latch for Bitlines inp
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7.2.5 Power Multiplexer Figure 7-16
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The inverter pair connected to the
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7.2.7 Memory Bank Architecture Figu
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7.2.8 Memory Bank Simulation Figure
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(Vpp) and a normal voltage (Vdd), t
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8.1.2 Dynamic Decoder The address d
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8.3 POWER-ON RESET One problem with
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Figure 8-6 shows the modified charg
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To study the impact of the power co
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9.0 CONCLUSION For this thesis, I h
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definitions, metal layer resistance
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APPENDIX B element standard cell ch
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$k=-1; $j=-1; $i=-1; foreach $ load
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$FALL_START_8 = $OFFSET8 + $ONTIME;
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if ($#rise_power_6 == -1) { # $modi
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$modified_spice_array[$i] = $temp2;
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@fall_power_9 = grep(/fall_power9/,
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print MEASHANDLE $_; print ENERGYHA
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} print MEASHANDLE " "; print ENERG
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set VAL [expr "$NUMBER_OF_MODULES_P
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set DIE_WIDTH_STRIPE [expr {($MODUL
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#*************************PLACING i
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preassignPin stripe $PIN_NAME -loc
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set X_LOC [expr {($X _LOC -( 31*$OU
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#Module related details set NUMBER_
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set X_LOC 0 set Y_LOC 41.2 for {set
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Table D 1 (Continued) 506.232fF 0.0
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121.344fF 0.076ns 0.4634 0.2277 570
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Table D 5 (Continued) 9.48 0. 516 0
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Table D 7: Characterization data fo
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Transi tion Table D 9: Characteriza
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[13] M.F. Aburdene, J. Zheng, and R
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i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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