i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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CONTROL PINS PREDICATOR INPUT DATA INPUT DATA INPUT INP1[31:0] INP2[31:0] ALU MODULE OUTPUT[31:0] DATA OUTPUT Figure 2-2: ALU Logical Diagram 2.3 INTERCONNECT MULTIPLEXER STRUCTURE (MUX) The multiplexer implements the interconnect structure used to connect the computational stripes. One possible interconnect structure called 5:1 is shown in Figure 2-3. The 5:1 interconnect structure is basically a 5:1 multiplexer that is emulated using 4:1 multiplexers. The 5:1 multiplexer is undesirable from a power and performance perspective. Hence it is good to emulate the behavior using 4:1 multiplexers. The ALU has three operands, INP1, INP2 and the predicator input. Each operand of the ALU has a multiplexer associated with it. The multiplexer for operand INP1 selects from ALU0, ALU1, ALU2 or ALU3. The multiplexer for operand 10
INP2 selects from ALU1, ALU2, ALU3 or ALU4. The multiplexer for the predicator input is similar to the one for operand INP2. Figure 2-3: 5:1 MUX Interconnect Structure 2.4 FINAL MULTIPLEXER STRUCTURE (FINALMUX) The third component of the hardware fabric is the FINALMUX stripe which is again a multiplexer stripe. The output of the fabric is physically connected to the output of the FINAL MUX stripe. A 4:1 FINALMUX stripe selects one out of four outputs. Let us consider a 20X18 RHF configuration with a 4:1 FINALMUX stripe and an ALU Stripe spacing of 4 as an example. For a 20X18 configuration having 18 computational stripes, the outputs can actually be derived from ALU stripe 6, ALU stripe 10, ALU stripe 14 and ALU stripe 18 for an ALU stripe spacing 11
Page 1 and 2: A PHYSICAL IMPLEMENTATION WITH CUST
Page 3 and 4: A PHYSICAL IMPLEMENTATION WITH CUST
Page 5 and 6: 4.0 ASIC DESIGN FLOW ..............
Page 7 and 8: 6.5.5 Characterization Results for
Page 9 and 10: LIST OF TABLES Table 5-1: ALU Modul
Page 11 and 12: LIST OF FIGURES Figure 1-1: SuperCI
Page 13 and 14: Figure 5-20: BIGFABRIC Logical Diag
Page 15 and 16: Figure 7-4: EEPROM Erase Physical O
Page 17 and 18: ACKNOWLEDGEMENTS “Many, O Jehovah
Page 19 and 20: 1.0 INTRODUCTION Technological adva
Page 21 and 22: Property) block. The physical desig
Page 23 and 24: the thesis proposes a power gated m
Page 25 and 26: 2.0 SUPERCISC RECONFIGURABLE HARDWA
Page 27: The specifications of the hardware
Page 31 and 32: 3.0 POWER ESTIMATION The need for e
Page 33 and 34: 3.1.1 Static Power Consumption Stat
Page 35 and 36: Internal Power Internal Power is th
Page 37 and 38: Switching activity Generation Switc
Page 39 and 40: Figure 3-4: Leakage Power definitio
Page 41 and 42: The entire array contains informati
Page 43 and 44: 3.3.2 Calculation of Fall Power Fig
Page 45 and 46: Figure 3-10: Off-state leakage Powe
Page 47 and 48: Figure 4-1 : Typical ASIC Design Fl
Page 49 and 50: Figure 4-2: ASIC Physical Design Fl
Page 51 and 52: 4.1.2 Powerplanning Power planning
Page 53 and 54: created in the design. Routing feed
Page 55 and 56: 4.1.7 Routing Once the standard cel
Page 57 and 58: Table 5-1: ALU Module Specification
Page 59 and 60: Table 5-2 shows the important speci
Page 61 and 62: the basic parameters are specified,
Page 63 and 64: direction have to be aligned on the
Page 65 and 66: ALU Stripe Pin Assignment The “ib
Page 67 and 68: 5.2.1 MUX Module Specifications As
Page 69 and 70: Figure 5-12: MUX Stripe Logical Dia
Page 71 and 72: MUX initialization routine The MUX
Page 73 and 74: Table 5-10: MUX Stripe Pin Placemen
Page 75 and 76: Figure 5-15: FINALMUX Module Logica
Page 77 and 78: Table 5-12: Final MUX Stripe Specif
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pins in the FINALMUX stripe is plac
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larger system. Figure 5-22 shows th
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Figure 5-20: BIGFABRIC Logical Diag
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Figure 5-22: Place and Routed BIGFA
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BIGFABRIC Stripe Pin Assignment As
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The SPEF file can be generated usin
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5.5.1 Power Results for ADPCM Encod
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5.5.3 Power Results for IDCT Row Be
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5.5.5 Power Results for Sobel Bench
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6.0 DELAY ELEMENTS FOR LOW POWER FA
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Transmission gate with Schmitt Trig
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PMOS transistors have their gate in
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output normally. The signal integri
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m-Transistor Cascaded Inverter This
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6.2 LOW POWER FABRIC USING DELAY EL
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The use of delay elements in the ha
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6.3.2 Dynamic Triggering Scheme A d
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Figure 6-16 shows the shunt current
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td1 is the delay in discharging nod
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δt is the regeneration time of the
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transistors, they are active low si
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delay elements are enabled on a log
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charge sharing happens between the
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Figure 6-23: AND gate to generate D
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uffer with a drive capacity of 640f
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Cell Rise Delay The Cell Rise Delay
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Fall Transition Time The time taken
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6.5.6 Characterization Results for
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7.0 EEPROM CIRCUIT DESIGN EEPROM (E
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7.1.1 Erase Operation Figure 7-3: I
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7.1.2 Write Operation Figure 7-6: I
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Figure 7-9: IV Characteristics of a
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The current source IFN, resistor RT
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Figure 7-11: HSPICE Description of
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7.2.1 Ramp Generator The ramp gener
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7.2.4 Column Latch for Bitlines inp
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7.2.5 Power Multiplexer Figure 7-16
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The inverter pair connected to the
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7.2.7 Memory Bank Architecture Figu
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7.2.8 Memory Bank Simulation Figure
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(Vpp) and a normal voltage (Vdd), t
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8.1.2 Dynamic Decoder The address d
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8.3 POWER-ON RESET One problem with
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Figure 8-6 shows the modified charg
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To study the impact of the power co
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9.0 CONCLUSION For this thesis, I h
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definitions, metal layer resistance
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APPENDIX B element standard cell ch
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$k=-1; $j=-1; $i=-1; foreach $ load
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$FALL_START_8 = $OFFSET8 + $ONTIME;
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if ($#rise_power_6 == -1) { # $modi
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$modified_spice_array[$i] = $temp2;
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@fall_power_9 = grep(/fall_power9/,
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print MEASHANDLE $_; print ENERGYHA
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} print MEASHANDLE " "; print ENERG
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set VAL [expr "$NUMBER_OF_MODULES_P
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set DIE_WIDTH_STRIPE [expr {($MODUL
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#*************************PLACING i
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preassignPin stripe $PIN_NAME -loc
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set X_LOC [expr {($X _LOC -( 31*$OU
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#Module related details set NUMBER_
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set X_LOC 0 set Y_LOC 41.2 for {set
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Table D 1 (Continued) 506.232fF 0.0
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121.344fF 0.076ns 0.4634 0.2277 570
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Table D 5 (Continued) 9.48 0. 516 0
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Table D 7: Characterization data fo
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Transi tion Table D 9: Characteriza
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[13] M.F. Aburdene, J. Zheng, and R
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