i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

8.1.1 Memory Block with Power Gate
Figure 8-2: Power Gated Memory Design
The primary benefit of the ``power gated'' implementation is that both the static and dynamic
power can be eliminated from all but the active memory block. The addition of a series power
enable PMOS device does not affect the average power consumed by the device, but reduces the
peak power consumed by the device. This technique has been previously applied to I/O buffers
to reduce the SSN (simultaneous switching noise) produced on the supply lines when the output
buffers switch [29]. The design implication with the reduction of peak power consumed by the
device is the on-chip regulator’s efficiency can be improved. As EEPROMS typically operate at
a low frequency, the addition of the PMOS device does not have an adverse impact on the speed
of the memory. However, the width of the power enable PMOS device should
be large enough to
suppl y enough
current during the normal operation of the memory.
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