i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

Dynamic triggering prevents shunt current that would cause higher power consumption
and spike noise on the power line [17]. But this requires an internal delay element τ for dynamic
timing generation [17]. The delay τ is required for disconnecting the path between Vdd and
ground using the Penable and Nenable signals. The delay τ can be generated using an inverter
chain. The delay between the input and output is not affected by the internal delay τ required for
generating the Penable and Nenable signals [17].
6.3.3 Static Triggering Scheme
A simpler version of the dynamic triggering scheme is the static triggering scheme [17] shown in
Figure 6-15. The static triggering scheme avoids the generation of Penable and Nenable signals
and this causes shunt current in the design.
D
Ictrl
VDD
Q Q
Figure 6-15: CMOS Thyristor Static Triggering Scheme
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