i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...
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5.5.4 Power Results for IDCT Column Bench Mark<br />
Table 5-20 summarizes the power consumed by the chip for every stripe in the SuperCISC<br />
reconfigurable hardware fabric design when the IDCT (Inverse Discrete Cosine Transform)<br />
Column bench mark was run on the fabric. The pre-layout power consumption of the chip was<br />
13.995mW and the post-layout power consumption was 19.979mW.<br />
Stripe<br />
Number<br />
Table 5-20: IDCT Col Post Layout Power Simulation<br />
Pre-Layout<br />
Power (uW)<br />
ALU Stripe MUX Stripe<br />
Post-Layout<br />
Power(uW)<br />
Pre-Layout<br />
Power (uW)<br />
Post-Layout<br />
Power(uW)<br />
S1 1109 1607 168.5 247.2<br />
S2 938.1 1511 164.1 251.1<br />
S3 504.3 638.9 193.1 294.2<br />
S4 505.6 595.7 163.1 234.7<br />
S5 455.2 599.1 165.5 248.2<br />
S6 495.4 629.9 179.7 272<br />
S7 550 657.6 214.3 314.5<br />
S8 617 734.1 188.6 288.9<br />
S9 1537 3000 202.5 309<br />
S10 605.2 764.2 253.2 378.2<br />
S11 682.3 892.5 290.5 426.6<br />
S12 820.7 993.7 329.7 492.1<br />
S13 911.6 1197 366.9 532.7<br />
S14 808.6 1041 321.1 451.7<br />
S15 153.8 155.5 0.1199 0.1199<br />
S16 2.307 2.307 0.1199 0.1199<br />
S17 2.307 2.307 0.1199 0.1199<br />
S18 2.307 2.307 93.26 213.5<br />
Total Power<br />
(uW) 10700.72 15024.12 3294.42 4954.96<br />
76