i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER EXTENSIONS
OF A RECONFIGURABLE HARDWARE FABRIC
Gerold Joseph Dhanabalan, M.S.
University of Pittsburgh, 2008
The primary focus of this thesis is on the physical implementation of the SuperCISC
Reconfigurable Hardware Fabric (RHF). The SuperCISC RHF provides a fast time to market
solution that approximates the benefits of an ASIC (Application Specific Integrated Circuit)
while retaining the design flow of an embedded software system. The fabric which consists of
computational ALU stripes and configurable multiplexer based interconnect stripes has been
implemented in the IBM 0.13um CMOS process using Cadence SoC Encounter.
As the entire hardware fabric utilizes a combinational flow, glitching power consumption
is a potential problem inherent to the fabric. A CMOS thyristor based programmable delay
element has been designed in the IBM 0.13um CMOS process, to minimize the glitch power
consumed in the hardware fabric. The delay element was characterized for use in the IBM
standard cell library to synthesize standard cell ASIC designs requiring this capability such as the
SuperCISC fabric. The thesis also introduces a power-gated memory solution, which can be used
to increase the size of an EEPROM memory for use in SoC style applications. A macromodel of
the EEPROM has been used to model the erase, program and read characteristics of the
EEPROM. This memory is designed for use in the fabric for storing encryption keys, etc.
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