i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

Property) block. The physical design flow actually transforms the synthesized design into the
layout that gets fabricated. Proper design considerations at the layout level are of utmost
importance for the commercial success of the IP block.
The pre-layout power characteristics of the IP block, estimated after synthesizing the
Verilog/VHDL netlist can use wireload models to model the interconnect parasitics. Such a
model could be pessimistic or optimisitic dependent on the vendor library. For an accurate power
estimation it is necessary to calculate the power consumed by the chip after placement and
routing of the chip has been completed. Also, as the RHF has interconnects which are
reconfigurable, it is necessary to understand the power consumed by the interconnects. Hence it
is of prime importance to do a post-layout power analysis.
As the objective of the SuperCISC reconfigurable hardware fabric (RHF) is to achieve a
low power reconfigurable solution, it is necessary to use custom circuit design techniques to
reduce any source of wasteful power consumption in the fabric. As the SuperCISC RHF uses a
complete combinational flow, glitching power is inherent to the fabric. The key design technique
that has been adopted is to freeze the inputs to the computational units using latches until all the
inputs to the computational unit have arrived. The latches are transparent (allow data to pass
through) when enabled and hold the previous value when disabled. The ‘enable’ input to these
latches is controlled by a delay element, which times the enabling of the latches. The value of the
delay element to be used is determined using STA (Static Timing Analysis) at the mapping stage
in the reconfigurable hardware fabric design flow. Hence, delay elements can be used to self-
time the design. However, conventional delay elements, like the inverter chain, transmission
gate, n or p-voltage controlled delay elements have a limitation on the range of delay that can be
obtained. Also the signal integrity of these delay elements is significantly degraded because of
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