i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

Transmission Gate Based Delay Element
A transmission gate (TG) based delay element has a NMOS and a PMOS connected in
parallel. The gates of the PMOS and NMOS are connected to GND and VDD respectively. The
delay in a TG based delay element is from the on-resistance of the parallel combination of the
PMOS and NMOS through which a load capacitance CL is charged and discharged. The on-
resistance of the delay element can be varied by adjusting the transistor sizes appropriately. The
reason for using both PMOS and NMOS in the structure is that a PMOS passes a logic high
value without degradation and a NMOS passes a logic low value without degradation.
The power consumed by the transmission gate delay element is from the charging and
discharging of the load capacitance. Hence the power consumed by the delay element is minimal.
However, because of the slow rise and fall times, the signal integrity of the delay element is
considerably degraded. In this context, signal integrity is said to be good when the rise and fall
times measured from 10% to 90% of the output is considerably small [15]. The delay element
cannot be used to generate large delay values because of the slow rise times. The slow rise and
fall times will cause a huge short circuit current consumption on the logic gate that is being
driven. The TG based delay element has shown to vary considerably with supply voltage
variations [11]. The TG can be used for delays in the range from 200-300ps [11]. Figure 6-1
shows the schematic of a transmission gate based delay element.
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