i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

P enable
Figure 6-18: CMOS Thyristor showing Parasitic Capacitances
Also mismatches between the current sources Ictrl and Ictrl` can cause the delays
between the rising edge to be different from the falling edge. As the delay element used for
timing the SuperCISC reconfigurable hardware fabric does not use a delay on the falling edge of
the signal, this effect is not pertinent to the application in hand.
An architecture modified to solve the above issues has been proposed by [18]. The
schematic of the modified CMOS thyristor delay element is shown in Figure 6-19. The signals
Qcharge and Q~charge are used to cancel the charge sharing effect. Qcharge is generated by the
NAND of inputs D and Nenable. Q~charge is generated by the NAND of inputs Dbar and PEN.
The prime motive in having signal Q~charge is to enable the PMOS transistor that can be used to
replenish the charge on node Q~ when PEN gets enabled. The signal Q~ charge needs to be
asserted low only as long as the D input is low. Hence, a NAND of inputs PEN and Dbar
accomplishes this purpose. Similarly Qcharge gets activated to replenish the charge on node Q
when NEN gets enabled. As the Qcharge and Q~charge are driving the gates of PMOS
100
N eable