i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

8.1.2 Dynamic Decoder
The address decoder to select the memory bank that needs to be enabled can be constructed using
static or dynamic CMOS circuits. Our design uses a dynamic CMOS gate with a pre-charge
transistor acting as the pull up network [6]. The dynamic decoder is a low-power alternative [30].
The pre-charge signal is driven by a periodic signal related
to the clock. In our case we can use
the system clock directly as the pre-charge signal. For a rising edge triggered memory, when
pre-charge is `1' the pre-charge PMOS transistor is off and the pre-charge NMOS transistor is on,
allowing the pull down network or evaluation
network to pull the appropriate power enable line
to ground, thus turning on the associated memory block. On the back half of the cycle, pre-
charge is '0' turning on the pre-charge PMOS and disconnecting the power enable line from
ground, thus turning off all the memory blocks.
The read power consumed during a read operation includes
the power required to
precharge the source terminal of the FLOTOX transistor, the power consumed by the sense
amplifier circuitry, and the row and column decoder power. The read operation is typically a low
voltage operation mode except for the word line boosting and bit line boosting schemes are used
to decrease the read time.
8.2 MEMORY BLOCK POWER CONSUMPTION
Many advanced low power circuit design techniques for Embedded EEPROMS have been
reported [24] [25]. The EEPROM power consumption can be categorized as 1) read power
consumption and 2) write power consumption.
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