i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

Figure 6-20: Timing diagram of the modified CMOS delay element
6.5 CUSTOM CMOS THYRISTOR DELAY ELEMENT FOR FABRIC
The original circuit of Figure 6-19 has been modified to suit the application needs of the
SuperCISC Reconfigurable Hardware Fabric. The circuit schematic of the delay element used in
the fabric is shown in Figure 6-21.
The delay element to be used in the SuperCISC reconfigurable hardware fabric, drives
the enable inputs of the latches. The latches when disabled, freeze the inputs to the
computational unit. The latches when enabled pass the inputs to the computational unit. The time
between the input to the hardware fabric and the valid output from the hardware fabric can be
considered as one processing cycle of the fabric. All latches used in the hardware fabric for
delaying the inputs are to disabled at the beginning of the processing cycle and need to be
enabled at the time points when they start the computation. All latches used in the context of
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