i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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set PIN_NUMBER [exp r " $START_PIN_NUMBER - $i"] set PIN_NAME "$THIRD_INPUT_NAME\\\[$PIN_NUMBER\\\]" puts "$PIN_NAME" preassignPin final_mux_stripe $PIN_NAME -loc $X_LOC $Y_LOC -layer 2 set X_LOC [expr "$X_LOC + $HOR_PIN_SPACING_TOP"] } set X_LOC [expr "$X_LOC + 7.2"] for {set i 0} {$i < 32} {incr i 1} { set PIN_NUMBER [expr "$START_PIN_NUMBER - $i"] set PIN_NAME "$FOURTH_INPUT_NAME\\\[$PIN_NUMBER\\\]" puts "$PIN_NAME" preassignPin final_mux_stripe $PIN_NAME -loc $X_LOC $Y_LOC -layer 2 set X_LOC [expr "$X_LOC + $HOR_PIN_SPACING_TOP"] } set val [expr "$MOD_NUMBER %2"] if {$val == 0} { set START_POSITION [expr " $START_POSITION + $INTER_MODULE_SPACING_MIN + $FINALMUX_WIDTH"] puts "MIN_SPACING\n" } else { set START_POSITION [expr "$START_POSITION + $INTER_MODULE_SPACING_MAX + $FINALMUX_WIDTH"] puts "MAX_SPACING\n" } } #End of outer for loop set START_POSITION 400 set Y_LOC $FINALMUX_STRIPE_HEIGHT for {set MOD_NUMBER $NUMBER_OF_FINALMUXES} {$MOD_NUMBER >0} {decr MOD_NUMBER 1} { set X_LOC $START_POSITION set START_PIN_NUMBER [expr "$MOD_NUMBER*32"] set START_PIN_NUMBER [expr "$ START_PIN_NUMBER -1"] for {set i 0} {$i < 32} {incr i 1} { set PIN_NUMBER [expr "$START_PIN_NUMBER - $i"] set PIN_NAME "final_output\\\[ $PIN_NUMBER\\\]" puts "$PIN_NAME" preassignPin final_mux_stripe $PIN_NAME -loc $X_LOC $Y_LOC -layer 2 set X_LOC [expr "$X_LOC + $HOR_PIN_SPACING_BOTTOM"] } set val [expr "$MOD_NUMBER %2"] if { $val == 0} { set START_POSITION [expr "$START_POSITION + $INTER_MODULE_SPACING_MIN + $FINALMUX_WIDTH"] } else { set START_POSITION [expr "$START_POSITION + $INTER_MODULE_SPACING_MAX +$FINALMUX_WIDTH"] } } 182
set X_LOC 0 set Y_LOC 41.2 for {set i 39} {$i > -1} {decr i 1} { set PIN_NAME "final_sel_bus\\\[$i\\\]" puts "$PIN_NAME" preassignPin final_mux_stripe $PIN_NAME -loc $X_LOC $Y_LOC -layer 5 set Y_LOC [expr "$Y_LOC - $VERT_PIN_SPACING"] } 183
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A PHYSICAL IMPLEMENTATION WITH CUST
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A PHYSICAL IMPLEMENTATION WITH CUST
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4.0 ASIC DESIGN FLOW ..............
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6.5.5 Characterization Results for
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LIST OF TABLES Table 5-1: ALU Modul
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LIST OF FIGURES Figure 1-1: SuperCI
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Figure 5-20: BIGFABRIC Logical Diag
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Figure 7-4: EEPROM Erase Physical O
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ACKNOWLEDGEMENTS “Many, O Jehovah
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1.0 INTRODUCTION Technological adva
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Property) block. The physical desig
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the thesis proposes a power gated m
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2.0 SUPERCISC RECONFIGURABLE HARDWA
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The specifications of the hardware
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INP2 selects from ALU1, ALU2, ALU3
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3.0 POWER ESTIMATION The need for e
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3.1.1 Static Power Consumption Stat
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Internal Power Internal Power is th
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Switching activity Generation Switc
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Figure 3-4: Leakage Power definitio
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The entire array contains informati
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3.3.2 Calculation of Fall Power Fig
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Figure 3-10: Off-state leakage Powe
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Figure 4-1 : Typical ASIC Design Fl
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Figure 4-2: ASIC Physical Design Fl
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4.1.2 Powerplanning Power planning
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created in the design. Routing feed
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4.1.7 Routing Once the standard cel
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Table 5-1: ALU Module Specification
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Table 5-2 shows the important speci
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the basic parameters are specified,
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direction have to be aligned on the
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ALU Stripe Pin Assignment The “ib
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5.2.1 MUX Module Specifications As
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Figure 5-12: MUX Stripe Logical Dia
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MUX initialization routine The MUX
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Table 5-10: MUX Stripe Pin Placemen
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Figure 5-15: FINALMUX Module Logica
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Table 5-12: Final MUX Stripe Specif
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pins in the FINALMUX stripe is plac
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larger system. Figure 5-22 shows th
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Figure 5-20: BIGFABRIC Logical Diag
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Figure 5-22: Place and Routed BIGFA
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BIGFABRIC Stripe Pin Assignment As
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The SPEF file can be generated usin
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5.5.1 Power Results for ADPCM Encod
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5.5.3 Power Results for IDCT Row Be
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5.5.5 Power Results for Sobel Bench
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6.0 DELAY ELEMENTS FOR LOW POWER FA
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Transmission gate with Schmitt Trig
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PMOS transistors have their gate in
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output normally. The signal integri
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m-Transistor Cascaded Inverter This
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6.2 LOW POWER FABRIC USING DELAY EL
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The use of delay elements in the ha
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6.3.2 Dynamic Triggering Scheme A d
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Figure 6-16 shows the shunt current
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td1 is the delay in discharging nod
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δt is the regeneration time of the
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transistors, they are active low si
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delay elements are enabled on a log
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charge sharing happens between the
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Figure 6-23: AND gate to generate D
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uffer with a drive capacity of 640f
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Cell Rise Delay The Cell Rise Delay
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Fall Transition Time The time taken
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6.5.6 Characterization Results for
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7.0 EEPROM CIRCUIT DESIGN EEPROM (E
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7.1.1 Erase Operation Figure 7-3: I
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7.1.2 Write Operation Figure 7-6: I
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Figure 7-9: IV Characteristics of a
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The current source IFN, resistor RT
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Figure 7-11: HSPICE Description of
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7.2.1 Ramp Generator The ramp gener
Page 149 and 150: 7.2.4 Column Latch for Bitlines inp
Page 151 and 152: 7.2.5 Power Multiplexer Figure 7-16
Page 153 and 154: The inverter pair connected to the
Page 155 and 156: 7.2.7 Memory Bank Architecture Figu
Page 157 and 158: 7.2.8 Memory Bank Simulation Figure
Page 159 and 160: (Vpp) and a normal voltage (Vdd), t
Page 161 and 162: 8.1.2 Dynamic Decoder The address d
Page 163 and 164: 8.3 POWER-ON RESET One problem with
Page 165 and 166: Figure 8-6 shows the modified charg
Page 167 and 168: To study the impact of the power co
Page 169 and 170: 9.0 CONCLUSION For this thesis, I h
Page 171 and 172: definitions, metal layer resistance
Page 173 and 174: APPENDIX B element standard cell ch
Page 175 and 176: $k=-1; $j=-1; $i=-1; foreach $ load
Page 177 and 178: $FALL_START_8 = $OFFSET8 + $ONTIME;
Page 179 and 180: if ($#rise_power_6 == -1) { # $modi
Page 181 and 182: $modified_spice_array[$i] = $temp2;
Page 183 and 184: @fall_power_9 = grep(/fall_power9/,
Page 185 and 186: print MEASHANDLE $_; print ENERGYHA
Page 187 and 188: } print MEASHANDLE " "; print ENERG
Page 189 and 190: set VAL [expr "$NUMBER_OF_MODULES_P
Page 191 and 192: set DIE_WIDTH_STRIPE [expr {($MODUL
Page 193 and 194: #*************************PLACING i
Page 195 and 196: preassignPin stripe $PIN_NAME -loc
Page 197 and 198: set X_LOC [expr {($X _LOC -( 31*$OU
Page 199: #Module related details set NUMBER_
Page 203 and 204: Table D 1 (Continued) 506.232fF 0.0
Page 205 and 206: 121.344fF 0.076ns 0.4634 0.2277 570
Page 207 and 208: Table D 5 (Continued) 9.48 0. 516 0
Page 209 and 210: Table D 7: Characterization data fo
Page 211 and 212: Transi tion Table D 9: Characteriza
Page 213 and 214: [13] M.F. Aburdene, J. Zheng, and R
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