i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

Figure 7-15 is asserted for a short duration of time. When LOAD gets asserted, the new
data value that needs to be written into the EEPROM cell gets loaded into the latch and the value
is stored at node X by the cross coupled inverter even after LOAD gets de-asserted. Under
normal conditions, DIS_BL_CTRL gets asserted and signal IN2 is asserted and signal IN1 is de-
asserted pulling the output of the level shifter to Vpp. This effectively turns off the pass
transistor connected to the bit line. When the data needs to be programmed into the EEPROM
cell, DIS_BL_CTRL gets de-asserted and DATA_CTRL is asserted. This loads the data into
nodes IN2 and IN1. Depending on the value of IN2 and IN1, the level shifter either discharges or
charges to enable the pass transistor as shown in Figure 7-16. The enabling of the pass transistor
connects the programming voltage to the bit line and the disabling of the pass transistor tri-states
the bitline. For an EEPROM cell to be programmed the pass transistor is enabled and the bit line
is connected to the programming ramp generated by the ramp generator as described in the
section 7.2.2. The DIS_BL, shown in Figure 7-16 is asserted to pull the BL node to ground
during an erase operation. The DIS_BL can also be asserted during a read operation to discharge
any unwanted voltages that get coupled to the bit line.
Figure 7-15: Data Latch Schematic of Column Latch
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