i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

6.3.2 Dynamic Triggering Scheme
A dynamic triggering scheme [17] based delay element using the CMOS Thyristor is shown in
Figure 6-14. The delay element uses two CMOS thyristors, the left half and the right half. The
left half CMOS thyristor ensures delay on the rising edge of D and the right half ensures the
delay on the falling edge of D considering Q as the output. Also the two CMOS thyristors help to
restore the charge on the nodes Q and Q~. To be specific, let us consider Figure 6-13. Once node
Q~ gets discharged, the standalone CMOS thyristor does not have a way to restore the charge on
node Q~ for the next cycle. The two CMOS thyristors help to avoid this situation. Also the
signals PENABLE and NENABLE help to avoid the shunt current condition during activation
[17].
Figure 6-14: CMOS Thyristor Dynamic Triggering Scheme
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