i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

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To meet the design requirement of having an undelayed falling edge, the current source required to discharge Q has been replaced with an NMOS transistor. The NMOS transistor M17 gets enabled when D input makes a transition from a logic high to a logic low. The NMOS transistor discharges node Q at a fast rate and hence the delay element does not have a delay on the falling edge of the signal. Input Vctrl of transistor M11 acts as the current source for the delay element. The signal Vctrl is generated from a constant gm based current source circuit and the transistor M11 mirrors the current. The current source used in the design is based on a 100nA current source. 6.5.1 Programmability For a 20X18 ALU configuration of the hardware fabric, there would be 360 ALU nodes (assuming homogeneous ALU configuration).The delay elements that are used can have value of 4ns, 5ns and 7ns, which totals to 3 delay elements per ALU node. Use of 3 delay elements per ALU node makes the number of delay elements used in the fabric to be around 3*360. The use of so many delay elements is prohibitive from an area perspective. So the idea of using a programmable delay element based on scaling the current source helps to overcome the overhead in having multiple delay elements. This programmability reduces the number of delay elements from 1080 to 360. One possible configuration would be to scale the input current mirror transistor connecting to signal Vtrl by having multiple PMOS transistors in parallel with enable switches connected to them in series. The major drawback behind this application is from the fact that the sizes of the input current mirror transistors are large. So, when the D input is off, charge gets stored on the drains of the large current mirror transistors and when the D input gets turned ON 104
charge sharing happens between the drain of the current mirror transistor and the drain of the diode connected NMOS transistor. This charge sharing causes a huge current to be mirrored on the path that discharges Q~. This limits the range of delay that can be achieved with the programmable delay element. An alternative solution that has been used is to scale the current mirror transistors in the path that discharges Q~. The inputs C0,C1,C2 connected to the gates of the NMOS transistors M22,M24 and M26 as shown in Figure 6-22 act as control switches that can be turned ON to scale the discharging current. As the switches are statically configured before the start of operation, the appropriate switches are always ON or always OFF. Using this approach, a well- controlled delay range has been obtained. The use of programmable current mirrors comes at the expense of an increase in the gate capacitance seen at the gate of the diode connected NMOS transistor M13. Under normal operating conditions, when D is turned ON, the gate of the diode-connected transistor rises to a potential depending on the charging current. When D gets turned OFF, the gate gets discharged to the threshold voltage of the diode connected NMOS transistor. With the increase in the gate capacitance, the time to discharge the node to Vtn (threshold voltage of NMOS) becomes higher. Also, during this time as Q~ gets replenished through Q~charge transistor M9, a static current path exists between node Q~ and ground because of the potential being above the Vtn of the NMOS transistors. Even under normal operating conditions, when D is OFF, the Vtn voltage on the diode-connected NMOS causes sub-threshold current leakage from node Q~ to ground. To alleviate this problem, an additional NMOS transistor M19 has been added with the drain connected to the gate of the diode-connect NMOS and the source connected to ground. The gate of transistor M19 is connected to dbar (D after inverted). So, when D is OFF, dbar gets enabled 105
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A PHYSICAL IMPLEMENTATION WITH CUST
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A PHYSICAL IMPLEMENTATION WITH CUST
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4.0 ASIC DESIGN FLOW ..............
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6.5.5 Characterization Results for
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LIST OF TABLES Table 5-1: ALU Modul
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LIST OF FIGURES Figure 1-1: SuperCI
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Figure 5-20: BIGFABRIC Logical Diag
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Figure 7-4: EEPROM Erase Physical O
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ACKNOWLEDGEMENTS “Many, O Jehovah
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1.0 INTRODUCTION Technological adva
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Property) block. The physical desig
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the thesis proposes a power gated m
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2.0 SUPERCISC RECONFIGURABLE HARDWA
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The specifications of the hardware
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INP2 selects from ALU1, ALU2, ALU3
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3.0 POWER ESTIMATION The need for e
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3.1.1 Static Power Consumption Stat
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Internal Power Internal Power is th
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Switching activity Generation Switc
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Figure 3-4: Leakage Power definitio
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The entire array contains informati
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3.3.2 Calculation of Fall Power Fig
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Figure 3-10: Off-state leakage Powe
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Figure 4-1 : Typical ASIC Design Fl
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Figure 4-2: ASIC Physical Design Fl
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4.1.2 Powerplanning Power planning
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created in the design. Routing feed
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4.1.7 Routing Once the standard cel
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Table 5-1: ALU Module Specification
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Table 5-2 shows the important speci
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the basic parameters are specified,
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direction have to be aligned on the
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ALU Stripe Pin Assignment The “ib
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5.2.1 MUX Module Specifications As
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Figure 5-12: MUX Stripe Logical Dia
Page 71 and 72: MUX initialization routine The MUX
Page 73 and 74: Table 5-10: MUX Stripe Pin Placemen
Page 75 and 76: Figure 5-15: FINALMUX Module Logica
Page 77 and 78: Table 5-12: Final MUX Stripe Specif
Page 79 and 80: pins in the FINALMUX stripe is plac
Page 81 and 82: larger system. Figure 5-22 shows th
Page 83 and 84: Figure 5-20: BIGFABRIC Logical Diag
Page 85 and 86: Figure 5-22: Place and Routed BIGFA
Page 87 and 88: BIGFABRIC Stripe Pin Assignment As
Page 89 and 90: The SPEF file can be generated usin
Page 91 and 92: 5.5.1 Power Results for ADPCM Encod
Page 93 and 94: 5.5.3 Power Results for IDCT Row Be
Page 95 and 96: 5.5.5 Power Results for Sobel Bench
Page 97 and 98: 6.0 DELAY ELEMENTS FOR LOW POWER FA
Page 99 and 100: Transmission gate with Schmitt Trig
Page 101 and 102: PMOS transistors have their gate in
Page 103 and 104: output normally. The signal integri
Page 105 and 106: m-Transistor Cascaded Inverter This
Page 107 and 108: 6.2 LOW POWER FABRIC USING DELAY EL
Page 109 and 110: The use of delay elements in the ha
Page 111 and 112: 6.3.2 Dynamic Triggering Scheme A d
Page 113 and 114: Figure 6-16 shows the shunt current
Page 115 and 116: td1 is the delay in discharging nod
Page 117 and 118: δt is the regeneration time of the
Page 119 and 120: transistors, they are active low si
Page 121: delay elements are enabled on a log
Page 125 and 126: Figure 6-23: AND gate to generate D
Page 127 and 128: uffer with a drive capacity of 640f
Page 129 and 130: Cell Rise Delay The Cell Rise Delay
Page 131 and 132: Fall Transition Time The time taken
Page 133 and 134: 6.5.6 Characterization Results for
Page 135 and 136: 7.0 EEPROM CIRCUIT DESIGN EEPROM (E
Page 137 and 138: 7.1.1 Erase Operation Figure 7-3: I
Page 139 and 140: 7.1.2 Write Operation Figure 7-6: I
Page 141 and 142: Figure 7-9: IV Characteristics of a
Page 143 and 144: The current source IFN, resistor RT
Page 145 and 146: Figure 7-11: HSPICE Description of
Page 147 and 148: 7.2.1 Ramp Generator The ramp gener
Page 149 and 150: 7.2.4 Column Latch for Bitlines inp
Page 151 and 152: 7.2.5 Power Multiplexer Figure 7-16
Page 153 and 154: The inverter pair connected to the
Page 155 and 156: 7.2.7 Memory Bank Architecture Figu
Page 157 and 158: 7.2.8 Memory Bank Simulation Figure
Page 159 and 160: (Vpp) and a normal voltage (Vdd), t
Page 161 and 162: 8.1.2 Dynamic Decoder The address d
Page 163 and 164: 8.3 POWER-ON RESET One problem with
Page 165 and 166: Figure 8-6 shows the modified charg
Page 167 and 168: To study the impact of the power co
Page 169 and 170: 9.0 CONCLUSION For this thesis, I h
Page 171 and 172: definitions, metal layer resistance
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APPENDIX B element standard cell ch
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$k=-1; $j=-1; $i=-1; foreach $ load
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$FALL_START_8 = $OFFSET8 + $ONTIME;
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if ($#rise_power_6 == -1) { # $modi
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$modified_spice_array[$i] = $temp2;
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@fall_power_9 = grep(/fall_power9/,
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print MEASHANDLE $_; print ENERGYHA
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} print MEASHANDLE " "; print ENERG
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set VAL [expr "$NUMBER_OF_MODULES_P
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set DIE_WIDTH_STRIPE [expr {($MODUL
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#*************************PLACING i
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preassignPin stripe $PIN_NAME -loc
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set X_LOC [expr {($X _LOC -( 31*$OU
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#Module related details set NUMBER_
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set X_LOC 0 set Y_LOC 41.2 for {set
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Table D 1 (Continued) 506.232fF 0.0
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121.344fF 0.076ns 0.4634 0.2277 570
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Table D 5 (Continued) 9.48 0. 516 0
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Table D 7: Characterization data fo
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Transi tion Table D 9: Characteriza
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[13] M.F. Aburdene, J. Zheng, and R
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