i A PHYSICAL IMPLEMENTATION WITH CUSTOM LOW POWER ...

m-Transistor Cascaded Inverter
This delay element has a cascode like structure with series connected PMOS and NMOS
in its pull-up and pull-down path respectively [15]. The gates of all these PMOS and NMOS
transistors are connected to the input. The cascode like structure has an increased ON-resistance
and capacitance. The additional capacitance arises from the diffusion capacitances of the source
and drain regions of the additional series transistors [15].
The m-transistor cascade has poor signal integrity because of the increased charging and
discharging resistance [15]. The power consumption is slightly higher than a simple inverter
chain because of the additional node capacitances in this structure.
Vin
Vdd
Vss
Vout
Figure 6-9: m-Transistor Cascaded Inverter
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